"On SRAM not scaling — yes, and it bounds the whole decode-to-SRAM threat. SRAM bitcell density essentially flatlined at N5→N3 (TSMC's high-density cell went from ~0.021 to ~0.0199 µm², ~5%, and N3E reportedly didn't move at all), while logic kept compounding ~1.6–1.7× a node. GAA/nanosheet at N2 gives a little back but nowhere near logic, and at much higher wafer cost — so SRAM $/bit doesn't improve, it degrades on advanced nodes as wafer prices climb"