Filter
Exclude
Time range
-
Near
Ben Stadler
@TheBenStadler
Jun 9
Replying to @cpucache
Fast
BridgeMind
@bridgemindai
Jun 9
I hit my usage limits on my $200/month Claude Max subscription in less than 30 minutes using Claude Fable 5.
142
IAmBullish
@iambullish
Jun 9
Replying to @cpucache @OnroyFelix @bcherny
no ultracode / max ? or 1M model ?
11
Vroble.com@Vroble_
May 30
Code crawling? 🐢 Cache misses kill perf! L1 hit ~1ns, RAM ~100ns . That's 100x slower! Optimize data locality. Stay in cache, stay fast. 🚀 #PerfEng #CPUCache #Coding
2
Shikhar
@xikhar
May 29
Replying to @cpucache
Yeah Opencode models are cheaper and better than that.
1
187
Shikhar
@xikhar
May 29
Replying to @cpucache
Don't tell me Opus is the new Haiku after Mythos is released.
1
6
5,139
Vroble.com@Vroble_
May 26
DRAM latency isn't fixed! 🤯 A single L3 cache miss can hit main memory anywhere from ~60ns to 300ns (2-5x fluctuation). Unpredictable perf killer under contention. #PerfEng #CPUCache #HardcoreDev 🚀
1
Vroble.com@Vroble_
May 21
Hardcore perf tip: Huge sequential writes killing your CPU cache? 🤯 Use non-temporal stores! Bypass L1/L2. Free up 20-50% cache bandwidth for hot data. Stop cache pollution & boost overall throughput! 🚀 #PerfEng #CPUCache
2
Vroble.com@Vroble_
May 4
Code crawling? 🐢 I-Cache misses hit HARD: 100-200 cycles each! Hot functions spread out = 15-25% perf loss. Optimize instruction locality! PGO helps. Keep functions small & grouped. 🚀 #PerfEng #CPUCache
2
Vroble.com@Vroble_
May 1
Perf killer alert! 💀 Your linker's code layout impacts I-cache. Scattered hot functions = 📉 cache misses. Group them with PGO linking for 5-15% speedup! 🚀 #PerfEng #Linker #CPUCache
9
Vroble.com@Vroble_
Apr 19
CPU perf killer: Cache Line Split Stores! 👻 Single write crossing a cache line boundary forces 2x cache ops. Costs 10-50 cycles! Align hot data. 🚀 #PerfEng #CPUCache
Vroble.com@Vroble_
Apr 12
CPU slow? 🐢 Cache associativity might be the hidden killer! L1 caches are set-associative. Conflicting data patterns can cause 10-20x slowdowns due to thrashing. Optimize data layout! 🚀 #PerfEng #CPUCache
Vroble.com@Vroble_
Apr 11
CPU decode stalls are real! 🤯 Complex instructions or bad code locality starve your CPU's pipeline. Favor single-μop instructions for hot paths. See 5-10% IPC boost by optimizing your instruction stream! 🚀 #PerfEng #CPUCache
7
Vroble.com@Vroble_
Apr 5
Memory alignment: Silent perf killer! 👻 Misaligned data costs CPU 2-4x more cycles. Optimize for aligned access & unlock hidden speed. 🚀 #PerfEng #CPUCache
1
Jakub Slys 🤖
@jakub_slys
Mar 12
L1, L2, L3: not just jargon—they’re the heartbeat of performance. Each cache level is bigger & slower than the last. Miss all three? It’s a long walk to RAM. How often do your programs make that trip? Read more: iam.slys.dev/p/cpu-caches-wh… #CPUCache #Programming #Computing #CodingMindset iam.slys.dev/p/cpu-caches-wh…

CPU Caches: Why tiny memory matters?

System design

iam.slys.dev
14
Vroble.com@Vroble_
Feb 18
Hidden CPU perf secret: the Micro-Op Cache! 🚀 Bypass slow instruction decoders by keeping hot loops tight. Can boost IPC 10-20%. Huge win for hardcore devs. #PerfEng #CPUCache
4
Vroble.com@Vroble_
Feb 11
CPU loops crawling? 🐢 Look for **Loop-Carried Dependencies**! Each iter needs previous result, forcing CPU to serialize. Kills pipeline perf, 10-20x slowdown! Break those deps for speed. 🚀 #PerfEng #CPUCache #Coding
6
Jakub Slys 🤖
@jakub_slys
Feb 8
Not all cache is created equal. Private L1/L2, shared L3, shifting policies—design matters, especially for concurrency. When did you last tune for hardware quirks? Read more: iam.slys.dev/p/cpu-caches-wh… #CPUCache #Concurrency #Optimization #Tech iam.slys.dev/p/cpu-caches-wh…

CPU Caches: Why tiny memory matters?

System design

iam.slys.dev
13
Vroble.com@Vroble_
Jan 26
I-Cache thrashing: The silent killer! 👻 Hot functions evicting each other's instructions slows CPU 15-25%. Optimize code layout. Boost throughput! 🚀 #PerfEng #CPUCache
3
Vroble.com@Vroble_
Jan 6
CPU perf secret: Store-to-Load Forwarding! 🚀 Loads get data directly from recent stores, bypassing L1 cache. But mismatched sizes/alignment BREAKS it, adding 5-20 cycles! Optimize memory access for raw speed. #PerfEng #CPUCache
15
Jakub Slys 🤖
@jakub_slys
30 Dec 2025
Associativity—Zen of cache line placement! Direct-mapped is simple but suffers conflict misses. Set-associative is the middle ground. Reflect on what makes your code cache-friendly. Read more: iam.slys.dev/p/cpu-caches-wh… #CPUCache #CodeOptimization #SoftwareEngineering #TechTalk iam.slys.dev/p/cpu-caches-wh…

CPU Caches: Why tiny memory matters?

System design

iam.slys.dev
16
Load more