As I read the MATCH Act and all the commentary on the subject of DUVi lithography restrictions, it's helpful to understand that the said "loophole"—multipatterning—is a fab production method dating back nearly 2 decades.
2008: Intel 45nm Logic used dedicated gate & cut masks, the first known use of multi-patterning lithography where a single layer is accomplished with 2 mask exposures.
2011: TSMC others 20nm Logic used Litho-Etch Litho-Etch (LELE) multipatterning with hard mask memorization for 64p metal.
2012: Samsung 20nm DRAM used Self-Aligned Double Patterning (SADP) cut mask for critical layers; later, this was applied to logic gate fin patterning, and eventually SAQP became mainstream across all advanced chip patterning.
2018: TSMC 7nm logic, before EUV source power hit 250W, 7nm production had already ramped using immersion LEx3-4 for contact, metal and via layers.
On this last point, up until 2018, when the first commercially viable EUV systems were shipped (NXE:3400B), the 7nm plan was to use immersion lithography with the NXT:2000i system. The only reason the plan changed was the magic number at the time, 250W. This was the source power that made EUV cheaper than 4-pass immersion.