I'm doing AI-assisted FPGA development. My new process is what excites me most, but the results are amazing too!
Claude:
- writes module unit tests in Icarus Verilog and debugs RTL
- Wires up module subsystems to build top-level system
- Builds a cycle-accurate model of the FPGA device using Verilator (.so)
- Builds a Python API for the device
- Writes system tests in Python
- Runs system tests against the cycle-accurate model and debugs RTL as necessary
- Creates Efinix project files (FPGA toolchain)
- Synthesizes RTL
- Uses timing reports to close timing, modifying RTL as necessary
- Uses resource reports to optimize for LUT, DSP, register, and BRAM usage
- Loads bitstream to physical hardware
- Runs Python system tests against the "hardware-in-the-loop" using memory-mapped IO (via PCIe)
- Iteratively debugs
As a concrete example, just in the last week and a half I did a first-principles re-implementation of a legacy MCU-based DSP algorithm (≈4000 LoC) in RTL (for an industrial sensor) using the process above. I'm already at nearly 100% test coverage and uncovered several minor bugs that went unnoticed for a decade. Oh, and I "vibe-coded" an oscilloscope tool to visualize the gigabit/sec sensor data coming in over PCIe using Dear PyGui.
The end result: reduction in compute hardware cost from $6.10/channel to $0.55 (~11× cheaper), with projected corporate profit increase of $555,000. And it's still January.