Final Year ECE @ HNBGU | @TRAI Intern | VLSI & Embedded Systems Enthusiast | Creative Techie | Photographer, Singer-Songwriter & Guitarist
Joined October 2021
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May 23
Spent days debugging instruction decoding,Built my custom pipelined MIPS processor on Basys 3 FPGA with a working dot-product accelerator.
After endless debugging, finally got the correct hardware output: 0032.
Now I want to make it dynamic and want to cnn in it can anyone help
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Jun 2
Hello everyone, myself Er. Sandeep Kumar
Electronics and Communication Engineer
Seeking job opportunities in VLSI, Embedded Systems, FPGA Design, and Digital Electronics.
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May 25
Implemented 2Γ2 Matrix Multiplication on a 32-bit 5-Stage Pipelined MIPS Processor using Verilog HDL on Basys 3 FPGA.
Successfully executed matrix operations with real-time FPGA output visualization using seven-segment displays.
#FPGA #Verilog #MIPS #VLSI #RTLDesign
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May 18
Show me your projects
I am making a mips 32 processor tell me how to make it representable π
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May 15
You don't have a better evening than me π. If you had the show me ??
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May 13
When was the last time you were happy? π₯ΉI bet you didn't have this beautiful view πͺ
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Mar 29
Tell me why this is a brilliant move π Check out this brilliant move: chess.com/analysis/game/liveβ¦
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Sandeep Kumar retweeted
Jan 12
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