Joined July 2018
- Tweets 63
- Following 24
- Followers 49
- Likes 2
4 Photos and videos
As part of @sochubfi, CPC successfully taped out a customized TTA-based Digital Signal Processor (DSP). "Beaivi DSP" was fully designed and C-programmed by using the OpenASIP tools developed by the group since the 2000s: tuni.fi/cpc/headsail_tapeout… @ITC_TampereUni
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The results of past 3 years of hard work on the edge AI offloading SW stack based on PoCL-R were shown in the AISA Y3 demo day last Friday. Feature showcase videos available (spoiler: Crazyflie can edge offload AI!): youtu.be/Rp6yeMuGh6s?si=o_yw… @vga_tuni @OpenCLorg @Bitcraze_se
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Link to the full playlist: youtube.com/playlist?list=PL…
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OpenASIP v2.1 released: github.com/cpc/openasip/rele…. It adds support for LLVM 17, speeds up DSE thanks to a more intelligent LLVM BE generation, and more! @sochubfi
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Customized Parallel Computing research group retweeted
30 Nov 2023
Our article introduces a dual-mode processor that utilizes ILP statically when available, without suffering from low code density when it's lacking. The architecture, supported by a novel compilation method, enables fine-grained mode switching. Read more: ieeexplore.ieee.org/document…
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Maarten Molendijk from @TUeindhoven presented "BrainTTA: A 28.6 TOPS/W Compiler Programmable Transport-Triggered NN SoC" in @ieee_iccd. BrainTTA was designed and programmed using the openasip.org tools. tuni.fi/cpc/#BrainTTA @sochubfi
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Customized Parallel Computing research group retweeted
4 Sep 2023
PoCL-R is a new backend for offloading OpenCL tasks to other nodes on the network. Now with OpenCL API offloading can be performed identically whether using local or remote devices - very interesting for adaptive edge offloading and other use cases! portablecl.org/remote-backen…
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HW accelerators require vendor-specific steps to use. A generic memory-mapped interface helps integrating them to a diverse OpenCL platform. Our interfacing work is now published in doi.org/10.1016/j.micpro.202… and the code available in the @portablecl repo! @openclapi @CPSoSAWARE
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Check a demo made with some of our final technical outcomes from the @CPSoSAWARE EU project: Nano-PoCL, PoCL-R and AlmaIF v2. Offloading OpenVX from a nanodrone to an FPGA using OpenCL as the offload API. Exciting stuff! youtu.be/GtNsznRk5jE @openclapi @portablecl
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OpenASIP 2.0 is out! It has the first #RISCV customization features, improved FU generation, LLVM 15, IP wrapping, among other new features! @sochubfi @CPSoSAWARE @openhwgroup openasip.org/release_2_0.htm…
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Customized Parallel Computing research group retweeted
18 Oct 2022
VLIW processors exploit ILP efficiently but suffer from bad code density in serial parts where instruction packets cannot be fully utilized. Read how we increased flexibility and energy efficiency by using both a TTA and RISC-V based ISA in one processor.
researchgate.net/publication…
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Customized Parallel Computing research group retweeted
18 Oct 2022
The open-standard RISC-V ISA has made the open source hardware community more active but there has been a lack of tools for customized RISC-V processors. Read how we added support for RISC-V based ASIPs to the upcoming 2.0 release of the OpenASIP toolset.
researchgate.net/publication…
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OpenASIP 1.25 is now out. It supports LLVM 14 and adds partial retargetable inline asm support and loop buffer compilation features. openasip.org/download.html Thanks to @CPSoSAWARE for supporting the @CustomParComp
group's contributions! @sochubfi @llvmorg
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Customized Parallel Computing research group retweeted
14 Oct 2021
Emerging memory technologies could enable extremely energy-efficient compute devices in the future. Read how domain wall memories can be utilized efficiently with our SHRIMP method.
ieeexplore.ieee.org/abstract…
@TampereUni @CustomParComp @cfaed_TUD @FitOptiVis @CPSoSAWARE
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OpenASIP 1.24 released! Adds LLVM 13 and first steps for Blocks CGRA support. openasip.org/download.html Thanks @FitOptiVis
@CPSoSAWARE @sochubfi for supporting the @CustomParComp group's contributions!
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A presentation about our ongoing work on PoCL-R: Distributed OpenCL Runtime for Low Latency Offloading available: youtu.be/Usj0CPC8zEs @portablecl @openclapi @FitOptiVis @CPSoSAWARE
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CPC is looking forward to contributing to this interesting joint project in its distributed high performance low latency computing aspects!
9 Jun 2021
Great news! @dimecc_fi facilitates the new AISA (AI based Situational Awareness) project!
The partners of the #AISAPROJECT are @nokia Technologies, @valmetglobal Automation, #Mirka, #Insta, @TopDataScience, @ficololtd and @TampereUni @BusinessFinland
dimecc.com/nokia-to-accelera…
OpenASIP 1.23 released! It's mainly a maintenance release that adds LLVM 12 support and removes support for older than LLVM 11 to clean up the code base. openasip.org/download.html Thanks @FitOptiVis @CPSoSAWARE @sochubfi
for supporting the @CustomParComp group's work!
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