Hardware implementations of high level functional programming languages. Supported by the EPSRC HAFLANG project at Heriot-Watt University (EP/W009447/1).
Here's a thread with the recorded YouTube talks from our HAFDAL workshop 👇
Starting with...
Carl-Johan Seger (Chalmers University of Technology) - The Cephalopode Project: Creating a low-power IoT device aimed at functional language execution.
youtube.com/watch?v=nn2AerR4…
We've curated a 100 year history of functional language hardware architectures. From 1924 to 2023.
This animated timeline is best viewed on a desktop or laptop.
haflang.github.io/history.ht…
Yukang Xie is presenting his research at TFP 2025 in Oxford. Draft paper title: "KappaMutor: A Compact Structured Combinator Processor for Haskell"
Yukang is a PhD student on our EPSRC HAFLANG project.
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HAFLANG - Functional Languages in Hardware retweeted
Some active and recent graph reduction projects, which implement functional programming languages directly in custom hardware.
A slide from Craig Ramsay's HAFLANG seminar talk at Chalmers University today.
Craig Ramsay is giving a project talk "Hardware Architectures for Lazy Functional Programming, Revisited" at SPLS at the University of Glasgow, 6th November.
spli.scot/spls/meetings/2024…
Yukang Xie, a new PhD student on this HAFLANG project, is investigating processor design for functional languages. His background is dataflow architectures for cryptography, and has developed an interest in functional languages and their implementations.
haflang.github.io/people.htm…
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HAFLANG - Functional Languages in Hardware retweeted
Our latest paper about Cloaca, an FPGA-based GC that uses hardware-level synchronisation and write barriers to avoid damaging graph reduction performance. We see significantly higher throughput and lower latency compared with a software GC implementation.
doi.org/10.1145/3677999.3678…
Our paper "Cloaca: A Concurrent Hardware Garbage Collector for Non-Strict Functional Languages" has been accepted to the Haskell Symposium 2024.
It combines mark-and-sweep tracing with one-bit reference counting. It runs concurrently to the mutator, both implemented in hardware.
Our IFL paper presents a processor for non-strict functional languages. By avoiding complex CPU circuitry and compiler indirections, it performs 6 times more reductions per cycle than GHC, competing with a 4.7GHz Intel CPU despite clocking at only 193MHz.
doi.org/10.1145/3652561.3652…
Here's a thread with the recorded YouTube talks from our HAFDAL workshop 👇
Starting with...
Carl-Johan Seger (Chalmers University of Technology) - The Cephalopode Project: Creating a low-power IoT device aimed at functional language execution.
youtube.com/watch?v=nn2AerR4…