Just measured my Linux-capable RISC-V SoC. ~2.2 CoreMark/MHz ~1.14 DMIPS/MHz That's roughly ARM9-class performance.

My custom RV32 Linux SoC is now roughly in 486DX4-100 territory: Linux 7.1, SV32 MMU, CoreMark 102, CPI 1.68.

Linux 7.1.0-rc2 running on my own RV32IMA SV32 KianV Stealth RISC-V SoC. CoreMark 102.07/50MHz, CPI 1.68 under Linux. Still a lot to optimize, but the platform is getting there.

Domain Sightings: Core-Mark and its dashed domain & brand 😀 domaingang.com/domain-news/d… #CoreMark #Brands #Domains #DomainSightings

Small evening rework on KianV StealthV. Now hitting 59.43 CoreMark @ 50 MHz (~1.19 CoreMark/MHz) and the SDRAM is finally running at 133 MHz BL=8 burst mode.

50 MHz, ~46 CoreMark, ~28.5 DMIPS. Roughly early 486SX-class performance already, despite still using a very primitive memory subsystem: single-beat SDRAM, simple direct-mapped caches, no real burst optimization yet.

用自主循环让 AI 编码代理对 RV32IM CPU 进行微架构锦标赛优化，仅当 CoreMark/MHz 超过当前冠军时才合并变更。 github.com/FeSens/auto-arch-… 把 AI 编码代理对准 SystemVerilog RV32IM CPU，每轮自动提假设、写 RTL、跑形式验证 协仿真 FPGA P&R，赢的合并，输的淘汰。73 个假设跑了近 10 小时，10 个通过，性能从 2.23 拉到 2.91 CoreMark/MHz，比 VexRiscv 高 26%，LUT 还少了 40%。项目反复强调：循环本身不值钱，验证器才值钱——63/73 被拒绝说明验证器硬气，结果才靠谱。

Bu da oldu: Yapay zeka 12 saatte işlemci tasarladı! 📌 Yonga tasarım girişimi Verkor-io, geliştirdiği "Design Conductor" adlı sistemle dikkat çekici bir başarıya imza attı. 📌 Şirketin açıklamasına göre bu yapay zekâ destekli sistem yalnızca 12 saat içinde tamamen sıfırdan bir RISC-V işlemci çekirdeği tasarladı. 📌 "VerCore" adı verilen yeni işlemci, spesifikasyondan üretime hazır GDSII tasarım dosyasına kadar tamamen otonom şekilde hazırlandı. 📌 VerCore'un teknik detaylarına bakıldığında, beş aşamalı boru hattına (pipeline) sahip, tek komutlu (single-issue) ve sıralı (in-order) bir mimari kullanıldığı görülüyor. 📌 İşlemci 1.48 GHz frekans hızına ulaşabiliyor. Performans tarafında ise CoreMark testinde 3.261 puan elde ettiği belirtiliyor. Bu sonuç, modern işlemcilerle rekabet edecek seviyede olmasa da giriş seviyesi eski sistemlere yakın. 📌 Buradaki en önemli nokta, sistemin klasik otomasyon araçlarından farklı çalışması. Design Conductor, büyük dil modellerini belirli kurallar çerçevesinde yönlendirerek tasarım, test ve optimizasyon süreçlerini uçtan uca tek başına yürütüyor. Yani süreç boyunca insan müdahalesi minimum seviyede tutuluyor. 📌 Proje henüz fiziksel olarak üretilmiş değil. Tasarım, Spike simülatörü üzerinde doğrulandı ve 7nm sınıfını temsil eden ASAP7 tasarım kitiyle geliştirildi.

💡 Predict before you implement. Thales built a precise performance model for the CVA6 RISC-V core to evaluate changes before touching RTL. The model achieved COREMARK performance results that were within 0.8% of the RTL, uncovering performance bottlenecks and informing the design of a dual-issue CVA6 core. Outcome? A 40% performance boost with just 7% power and 11% area. This shows how modeling can transform open hardware development. Explore the project here: hubs.la/Q04c5j7G0

...at the cost of 8 DSP48 cores and HALF of fmax, because the DSPs f*ck my beautiful hand optimized combinational path! anyway, that shows how weird is CoreMark with RV32I vs. RV32IM! 🤣

BREAKING: new M-extension on DarkRISCV enables increase of 137% on performance, according to CoreMark Benchmark! 🔥 github.com/darklife/darkrisc…

They also don't run central warehouse. So typically their main supplier would be a company like Coremark, or Sobey's. So if there's supply issues that's not really a Canex problem.

🔍 How do you accelerate real hardware innovation? Thales shows the power of performance modeling with the CVA6 RISC-V processor. Using a cycle-accurate Python model, they identified and tested performance improvements before RTL implementation, guiding the creation of a dual-issue CVA6 core. The result: 40% CoreMark/MHz with only modest increases in power and area. This is a clear example of modeling driving smarter hardware design. 👉Check out the short walkthrough video and the project: hubs.la/Q0482g6d0

TP-LINK 7DR7299 免拆刷 OpenWrt 记录分享！ ✅ 处理器：MT7988A (CoreMark 跑分 35688，约等于小米万兆 80%) ✅ 流程：原厂 -> Debug 固件 -> ImmortalWrt（有手就行） 🤖缺点一：内核缺少 kmod-tun，可恶啊 不能“养猫”，差评！ 🤢缺点二：原厂5G信号隔两堵墙还能跑千兆，刷机后只有600多Mbps了，WiFi 信号较原厂衰减约 40% 目前刷机可玩性一般，不推荐。 👉 详情：mao.fan/article/486 #OpenWrt #TPLINK #路由器 #WiFi7 #刷机

16 cores simulation with data-cache showing the pc value of each CPU while running CoreMark. For the most part, each core is able to execute an instruction every clock cycles.

I have promising simulation showing 50.2 Coremark/MHz using 16 cores or 3.1 Coremark/MHz/Core. With single core at 3.5 Coremark/MHz, performance increases almost linearly from 1 to 16 cores. I am still working to make all tests pass to make a release.

this is so fucking cool wha??? coremark score of 3200 is crazy