Joined February 2024
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23 Photos and videos
Complete HIL simulation verification achieved in GTKWave sim. Timeline tracking confirms raw PDM mic decimation, FFT anomaly extraction, and the resulting rising-edge FPGA interrupt to the host STM32H743.SPI register capture confirms successful 0x01 status parsing.#SystemVerilog
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AgriGuard-RES HDL simulation is live. Running a parallel co-design stack in iverilog: PDM mic decimation filter to 256-Point FFT accelerator.Caught the Fall Armyworm anomaly signature cleanly and now patching a few sticky register bits in the SPI slave. #SystemVerilog #FPGA
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Firmware bring-up is officially underway for AgriGuard-RES. Reviewing the autogenerated low-level HAL GPIO initialization structures in STM32CubeIDE.#STM32
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Locking down the clock matrix for AgriGuard-RES. Running the STM32H743IIT6 at its max 480 MHz SYSCLK using a 25 MHz HSE source. Custom PLL1 sequencing delivers a precise 240 MHz AXI bus while keeping peripheral clock domains tightly optimized for low power #EmbeddedSystems #STM32
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Cloud IoT fails where there is no grid or cell signal. Built AgriGuard-RES to solve this for #farmers in offgrids: an infrastructure-independent edge sentinel running local AI inference (STM32H7 Lattice iCE40 FPGA) to catch plant stress & pests in real time. #smartfarming
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Dense BGA escape routing on a 6-layer stackup completed. Off to fabrication
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6-layer edge sentinel for Agrionics Co. Lattice iCE40HX FPGA co-processor handles real-time sensor & mic array data, offloading heavy lifting from the STM32H7 so the MCU stays in low-power sleep. Sustained via ADP5090 solar harvesting &CR2032 backup with 868MHz data transmission.
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Scaling this out as a reconfigurable AI reference design. check the full documentation.
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Kept the antenna path completely straight from the SX1262 transceiver to the U.FL port to wipe out reflections. Also got a solid Layer 2 ground plane with tightly pitched stitching vias to cage the sub-GHz signals and protect the nearby FPGA fabric.
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@Sincerely, Stepper retweeted
Jun 1
Our #FMC Development Board in final Routing Stage 😎
It offers 8 Thunderbolt 5 (80Gbps) USB-C together with 2x100G Ethernet. Will support VITA FMC & HSPCe.
A huge #AMD #Versal #FPGA SoC will run as the heart of this monster.
#Aaronia #RFSOC
ALT Aaronia FMC Development Board PCB Routing
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144 MHz Halo Antenna
Construction and Analysis of a Low Cost Omni directional Horizontally Polarized Antenna for 144 MHz By: Dr. Carol F. Milazzo, KP4MD
Complete Details & More: qsl.net/kp4md/144_mhz_…
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Welp after spending a full *month* in customs queues, prototype fasterscope is finally in my hands and it's looking good!
Now i need to make time for soldering (impossible atm)
"about a week" turned into a month very quickly but it's about time to order fasterscope rev0.1
This a loong board: 163x43mm, and fairly complex: 350 components, 1500 pads, 1000 vias before stitching
I only did one channel for rev0.1 to keep it simple but otherwise this should be fully functional: able to scope at 800MSPS with a variable analog bandwidth up to 400MHz (down to 20MHz). It will stream all of this data over usb.
I'm very excited to receive this. I plan to solder it by hand to save ~3 weeks sending parts over to jlc and having them assemble it. I've come up multiple tricks to manually solder this as fast as possible and I plan to share more on that soon.
Thanks for sticking along for the ride
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@Sincerely, Stepper retweeted
May 27
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@Sincerely, Stepper retweeted
May 25
How many spectrum analyzers do you need?
Me: yes.
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Implementing some cognitive radio for my remote offgrid Edge Computing devices. Check out this spectrum sensing snippet.
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