Joined March 2009
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172 Photos and videos
luke k.c. leighton retweeted
3 Jul 2023
My newsletter has one subscriber. Me. Help me change that over on LinkedIn. Week 1 includes #AI, #biotech, #cleantech, #spacetech, and #semiconductors. Plus a touch of #SciFi. linkedin.com/newsletters/the…
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17 May 2023
indico.cern.ch/event/1231545… OSSYM2023 at @CERN 5th International Symposium on Open Search deadline is 31st May
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15 May 2023
it took me a while to notice that ARM has special instructions for linked-list-pointer-chasing alastairreid.github.io/paper… however i am delighted to confirm that SVP64 Vector instructions for linked-list-chasing works. @OpenPOWERorg
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luke k.c. leighton retweeted
4 May 2023
This is important work! Help ensure it continues by becoming a @BlockchainComns sponsor. [13/13] github.com/sponsors/Blockcha…
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luke k.c. leighton retweeted
4 May 2023
This week’s Silicon Salon 4 explored the challenges and offered some insights into solutions at the intersection of cryptography and semiconductor manufacturing. Explore the presentations by Andrew Poelstra, Red Semiconductor, and @cramiumlabs now! [1/13] siliconsalon.info/salon4/
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luke k.c. leighton retweeted
2 May 2023
Luke Leighton @lkcl & David Calderwood will overview the missing RISC ISA instructions related to biginteger operations [3/5]. x.com/ChristopherA/status/16…
1 May 2023
Most RISC ISA chip designs are missing instructions allowing for chaining to create vector results for biginteger operation used in cryptography. @lkct & David Calderwood will be talking on this topic at Silicon Salon 4, hosted by @BlockchainComns. 🧵[1/9] eventbrite.com/e/silicon-sal…
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29 Apr 2023
doing the write-up for OPF ISA WG External RFC ls016 - Integer Twin-Butterfly DCT/FFT "mul-add-sub-shift-imm" libre-soc.org/openpower/sv/t… the number of instructions it replaces is *eight*. and it's in-place. no temp regs. massive savings. @IBMResearch @OpenPOWERorg @GanesanBlue
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26 Apr 2023
with many thanks to @NgiSearch and @FundingBox we will be optimising the SVP64 Draft ISA (proposed to the @OpenPOWERorg ISA WG last week) for Search. VectorCamp will be porting VectorScan to SVP64, Vantosh optimising libc6 string/memory routines linkedin.com/feed/update/urn…
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10 Apr 2023
i'm writing up OpenPOWER ISA Working Group External RFCs full-time at the moment, to be proposed for the SFFS subset. right now i'm doing a "summary" document of future Draft Scalar instructions. feedback welcomed. thx to @NLnetFDN @OpenPOWERorg ftp.libre-soc.org/opf_ext_rf…
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13 Apr 2023
@GanesanBlue @mikeyneuling @antonblanchard @PCzanik @mpc7500v2 @gabor_samu @kanzure @jon_trossbach @jonmasters @blu51899890 @prozacchiwawa
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16 Apr 2023
SVP64 has now been formally submitted in full to the @OpenPOWERorg Foundation's ISA TWG. Comprising some 150 pages it needed splitting into five RFCs: ls001 PO9, ls005 XLEN, ls008 setvl/svstep, ls009 SVP64 and ls010 REMAP. libre-soc.org/openpower/sv/r…
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luke k.c. leighton retweeted
9 Apr 2023
> Meanwhile, the processor's stream performance with eight channels of DDR4-3200 memory crosses the 50GB mark.
Wow! /he exclaimed, while reading this article on an tablet-grade arm SoC doing 65GB/s of RAM BW
tomshardware.com/news/loongs…
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6 Apr 2023
thx christopher for the opportunity. i'd like to have also presented about the Vectorised chacha20 algorithm we did (all 20 rounds in 10 in-register parallel vector instructions, i.e. a single L1 Cache Line) but settled instead on biginteger operations. libre-soc.org/openpower/sv/b…
6 Apr 2023
Our next monthly call will coincide with Silicon Salon 4, with topics such key exfiltration prevention w/ @Blockstream's Andrew Poelstra, bigint in silicon w/ @lkcl, and discussion on open hardware requirements. eventbrite.com/e/silicon-sal… [10/12]
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6 Apr 2023
nutshell: we're proposing 3-in 2-out mul/div/shift ops that use one extra 64-bit reg as "carry-in carry-out". SVP64 "magically" chains them. operand fwd bus drops them down to 2-in 1-out (except 1st and last in chain). @jon_trossbach @geofflangdale git.libre-soc.org/?p=openpow…
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6 Apr 2023
the only other ISAs i know of that have this type of "large" carry (more than 1 bit carry-in/out) are Mitch Alsup's MyISA 66,000 and a really *really* early version of Power ISA (Power ISA 1 or so!) they had a 32-bit Carry-In/Out SPR, later dropped unfortunately. know any others?
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luke k.c. leighton retweeted
11 Feb 2023
Mathematics, programming, the universe.
The eternal uncoiling.
By Matthew Hughes, @tasty_plots, instagram.com/tasty_plots, Used with permission.
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