Don’t allow other IP suppliers to force one-size-fits-all cores into your design. Get the IP you need, tailored to your specs, with SmartDV: IP Your Way.

Joined October 2010
301 Photos and videos
JEDEC just raised the bar for storage. UFS 5.0 is out and SoC teams are already planning their next tapeout around it. SmartDV has the full stack covered. hubs.la/Q04kk9vW0 More links in comments. #SmartDV #UFS5 #SemiconductorIP
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SmartDV Design IP and Simulation VIP for UFS 5.0 -- find out more: smartdvtech.com/products/ufs… smartdvtech.com/products/ufs… smartdvtech.com/products/ufs…

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Two great days at #ChipEx2026 in Tel Aviv. Thanks to everyone who stopped by. #SmartDV
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We're at #ChipEx2026 in Tel Aviv. Stop by MosaIC's Booth E7 and say hi to Gary. #SmartDV
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Israel's semiconductor community comes together once a year at ChipEx, and SmartDV will be there on May 12–13 in Tel Aviv. Our Israel representative MosaIC will be representing SmartDV at Booth E7. Gary will be on-site and happy to connect. #ChipEx2026 #SmartDV #SemiconductorIP
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We’re at IP‑SoC Silicon Valley today and looking forward to talking semiconductor IP and verification. Stop by and connect! #IPSoCDays #SmartDV
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SmartDV is heading to IP-SoC Silicon Valley on April 23 in Santa Clara. Stop by to talk semiconductor IP and verification. #IPSoCDays #SmartDV
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Embedded World 2026 starts tomorrow in Nuremberg! 📍 Find us at Booth 4-476 📅 March 10 “Turning Up the Volume: How SoundWire I3S Transforms Embedded Audio” Technical session in collaboration with the MIPI Alliance. #EmbeddedWorld #SmartDV #SoundWire #I3S
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SmartDV is at DVCon U.S. today and tomorrow. Let’s talk Design IP Verification IP and practical SoC design & verification challenges. If you’re attending, let's connect! Stop by booth #105. #DVCon #SoC #Verification #EDA
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SmartDV at Embedded World 2026 (March 10–12, Nuremberg) 📍 Booth 4-476 📅 March 10 “Turning Up the Volume: How SoundWire I3S Transforms Embedded Audio” Technical session in collaboration with the MIPI Alliance. #EmbeddedWorld #SmartDV
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SmartDV IP is now available as validated system-level models in VisualSim®, starting with CXL. Enables early architectural exploration aligned with production RTL before implementation. More details: tinyurl.com/3m8ezbym #CXL #EDA #SoCDesign #SmartDV
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SmartDV will be exhibiting at DVCon U.S. 2026 (#105) next week in Santa Clara. Let’s talk Design IP Verification IP and practical SoC design & verification challenges. If you’re attending, let’s connect. #DVCon #SoC #Verification #EDA
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Live today at Chiplet Summit 2026 in Santa Clara - Booth 215. If you’re working on UCIe, CXL, PCIe, or chiplet-based system planning, let’s connect. #ChipletSummit #Chiplets
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SmartDV at Chiplet Summit 2026 (Feb 18–19, Santa Clara) - Booth 215. Working on UCIe, CXL, PCIe, or chiplet-based planning? Let’s connect! #Chiplets #SoC #PCIe #UCIe #CXL
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Our community and customers continue to inspire what we build and where we’re going. We're looking forward to a new year of innovation, collaboration, and shared success!
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Grateful for our community, partners, and customers. Happy Holidays from our team to yours!
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Throwback to ICCAD-Expo China 2025, where Sunray from SmartDV China shared insights on how customized Design IP, Verification IP, functional safety, and ecosystem collaboration enable next-gen intelligent device chip designs. #SmartDV #DesignIP #VerificationIP
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At IP-SoC Europe 2025, SmartDV is showcasing an FPGA-based hardware demo and providing information about its extensive product portfolio and latest additions. There is still an opportunity today to have a personal conversation with Philipp Jacobsohn and Dave Johnson. #SmartDV
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We're all set up at IP-SoC Europe 2025 in Grenoble! Stop by and connect with SmartDV Dec. 2-3 — we’re here to discuss innovative IP and verification solutions tailored for your next project. #SmartDV hubs.la/Q03WnFyw0
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There's still time to visit us at ICCAD-Expo China 2025. Stop by booth D91! #SmartDV hubs.la/Q03VlWg80
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