ALT Six tables showing the machine instructions for the atomic operations on ARMv8, ARMv8.1 and x86-64, for non-atomic, relaxed, acquire, release, acquire plus release, and sequentially consistent memory ordering. The six tables are labeled: load, store, swap, fetch op, compare exchange, fence. The full contents don't fit in the alt text, but here are the main takeaways: On x86, in each table, the instructions are the same for all (atomic) memory orderings, except seqcst store using a XCHG instruction instead of a MOV, and seqcst fence using MFENCE instead of nothing. On ARM, the acquire plus release instructions are equivalent to the sequentially consistent instructions in all cases. On ARMv8, the swap, fetch op and strong compare exchange are implemented as loops using the LDXR and STXR instructions. But on ARMv8.1, they are all implemented as a single instruction. On x86, fetch op is implemented with a lock prefix for some operations, and as a CMPXCHG loop for some others.

ALT auto_import::magic!(); fn main() { let _ = BTreeMap::<File, PathBuf>::new(); let _ = i32::from_str("123"); std::io::stdout().write_all(b"!\n").unwrap(); }

ALT $ cargo run Compiling auto_import v0.1.0 Compiling example v0.1.0 Injecting use std::collections::BTreeMap; Injecting use std::fs::File; Injecting use std::path::PathBuf; Injecting use std::str::FromStr; Injecting use std::io::Write; Finished dev [unoptimized debuginfo] target(s) in 0.47s Running `target/debug/example` !