This week was also special as we celebrated the 20th anniversary of our Shanghai R&D center and 10 years of partnership with TFME. So proud of our @AMD team and partners for all we’ve built together.

AMD’s EPYC Venice becomes industry’s first 2nm HPC CPU to achieve volume ramp as it races towards agentic AI leadership. wccftech.com/amd-epyc-venice…

This is a major scoop by @business confirming Nvidia’s Jensen Huang was not invited and will not participate in President Trump’s visit to China. The reality is that U.S. AI policy has hardened post-Mythos, and the Trump administration is taking competition with China extremely seriously. Thanks to @eastland_maggie for the chance to comment: “Keeping Huang off the official delegation list sends a strong signal to the government in Beijing that Chinese AI labs won’t have much success in obtaining top-performing chips like those made by Nvidia, according to Ryan Fedasiuk, a fellow at @AEI. ‘The Trump administration understands how important computing power is to winning the AI race with China,’ Fedasiuk said. ‘There just isn’t much for American chip companies to talk about with the Chinese government.’” bloomberg.com/news/articles/…

NVIDIA today, in one news cycle: Open-sourced Multipath Reliable Connection (MRC) through the Open Compute Project. Co-developed with Microsoft, OpenAI, AMD, Broadcom, Intel. Proven first on Spectrum-X Ethernet hardware. Already running in production at OpenAI, Microsoft Fairwater, and Oracle Abilene. Same morning, took $500M in Corning warrants. Right to invest up to $2.7B total. Corning expanding U.S. optical connectivity capacity 10x. U.S. fiber capacity up more than 50%. Three new plants in North Carolina and Texas. Same day. Not a coincidence. The so what: Copper has a physics ceiling. Beyond a certain reach and bandwidth density, you cannot push more bits without burning unacceptable power. Gigascale AI factories with hundreds of thousands of GPUs blew past that ceiling. Optical is no longer a niche scale-up choice. It is the substrate. MRC is the protocol layer. It assumes the fabric is lossy, multipath, and massive. It load-balances across every available path. It reroutes around failures in microseconds, in hardware. It keeps thousands of GPUs synchronized when a single brief stall can torch a frontier training run. Corning is the physical layer. Low-loss fiber, optical connectivity, photonics packaging. The bottleneck is no longer the chip. It is the glass between the chips. NVIDIA is doing what they always do. Define the protocol. Optimize the silicon to it. Open the spec once their hardware is the reference implementation. Then vertically integrate the supply chain so no one can choke them on the inputs. Memory Wars showed the world that bandwidth, not flops, was the bottleneck inside the rack. The next chapter is what happens between the racks. Hardware does not win alone. Software does not scale alone. Increasingly, neither wins without owning the photons.