@DevkotaL22 profile picture
Devkota Lenin @DevkotaL22
Joined May 2025
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  • Followers 5
75 Photos and videos
I learned how pipelining breaks down operations into sequential stages that execute concurrently, allowing new inputs to enter before previous ones complete reducing overall processing time. #verilog #NativesPlug #LearnInPublic #LOCUS2026 #15DayChallenge #NepalTech #LearnAndWin
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I learned how pipelining in Verilog works, breaking down complex operations into concurrent stages to achieve significant speedup with minimal hardware overhead. #NativesPlug #LearnInPublic #LOCUS2026 #15DayChallenge #NepalTech #LearnAndWin
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I successfully implemented and simulated a 16-to-1 multiplexer in Verilog using a hierarchical design approach with 4-to-1 mux building blocks. It is another step forward in my digital design. #NativesPlug #LearnInPublic #LOCUS2026 #15DayChallenge #NepalTech #LearnAndWin
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Today I learned how to design a Verilog-based finite state machine (FSM) sequence detector that detects the bit pattern “0110” using clocked state transitions and combinational next-state logic. #NativesPlug #LearnInPublic #LOCUS2026 #15DayChallenge #NepalTech #LearnAndWin
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I implemented a 3-state cyclic traffic light controller in verilog using a case-based FSM that transition through green → yellow → red state on each clock cycle, verified through GTKWave simulation. #NativesPlug #LearnInPublic #LOCUS2026 #15DayChallenge #NepalTech #LearnAndWin
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I made Verilog parity generator testbench that toggles the input signal x through various bit patterns and uses GTKWave to visualize the output signal z, which computes the parity of the 32-bit input. #NativesPlug #LearnInPublic #LOCUS2026 #15DayChallenge #NepalTech #LearnAndWin
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I successfully simulated and verified a 16-bit ALU adder circuit in Verilog today. I observed the expected waveform outputs in GTKWave for multiple test cases. #NativesPlug #LearnInPublic #LOCUS2026 #15DayChallenge #NepalTech #LearnAndWin
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I Implemented my first SR latch in Verilog .It is a fundamental memory element that uses cross-coupled NOR gates to store a single bit of state. #NativesPlug #LearnInPublic #LOCUS2026 #15DayChallenge #NepalTech #LearnAndWin
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I implemented 8-bit multiplier in Verilog using the repeated addition algorithm. It is a great example of converting algorithmic thinking into hardware design with datapath, control unit architecture. #NativesPlug #LearnInPublic #LOCUS2026 #15DayChallenge #NepalTech #LearnAndWin
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I built a 4-bit asynchronous reset counter in Verilog today. It is simple, functional, and a good reminder that sometimes the foundational digital design blocks are the most satisfying to implement. #NativesPlug #LearnInPublic #LOCUS2026 #15DayChallenge #NepalTech #LearnAndWin
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Explored Verilog memory modeling from simple reg arrays with initialization to parameterized RAM modules with r/w operations. It unlocks foundation for building efficient digital storage systems. #NativesPlug #LearnInPublic #LOCUS2026 #15DayChallenge #NepalTech #LearnAndWin
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Built and verified an 8-bit arithmetic shift right (ASR) module in Verilog using a testbench and GTKWave to confirm correct signed-number behavior. #NativesPlug #LearnInPublic #LOCUS2026 #15DayChallenge #NepalTech #LearnAndWin
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Dived into Verilog coding standards today like proper naming conventions, meaningful signal name, comprehensive file headers and synthesis-friendly coding practices that makes error free RTL designs. #NativesPlug #LearnInPublic #LOCUS2026 #15DayChallenge #NepalTech #LearnAndWin
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Explored Verilog synthesis fundamentals: understanding which constructs (continuous assignments, functions, for loops) translate to actual hardware vs. which create sequential circuits. #VLSI #NativesPlug #LearnInPublic #LOCUS2026 #15DayChallenge #NepalTech #LearnAndWin
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Built a 2:1 multiplexer using gate-level Verilog modeling. Simple yet fundamental selecting between two inputs with basic logic gates. Every complex chip starts with mastering these building blocks! #NativesPlug #LearnInPublic #LOCUS2026 #15DayChallenge #NepalTech #LearnAndWin
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#LSPPDay60 Today , I used Stacking Classifier ensemble method to the Heart Disease dataset to improve accuracy of heart disease prediction. It combines multiple base models and uses meta-model to make final predictions. @lftechnology #60DaysOfLearning2025 #LearningWithLeapfrog
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#LSPPDay59 Today , I attend a session on "Getting Started With Linux & Cybersecurity". It was really knowledgeable and interactive session. I learned , -Introduction to computer network -OSI model - Protocols @lftechnology #60DaysOfLearning2025 #LearningWithLeapfrog
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#LSPPDay58 Today , I learned about the different types of Hierarchical Clustering . Its basic ideas and how does this clustering works. - Agglomerative Hierarchical clustering - Divisive Clustering @lftechnology #60DaysOfLearning2025 #LearningWithLeapfrog
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#LSPPDay57 Today , I revised the concepts and algorithm that I learned in few days like: - Gradient Boosting Regressor - Gradient Boosting Classifier - Stacking - Blending @lftechnology #60DaysOfLearning2025 #LearningWithLeapfrog #MachineLearning
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#LSPPDay56 Today , I learned about K-fold approach in machine learning . It is used to estimate the performance of a model on unseen data and to evaluate its generalization ability. @lftechnology #60DaysOfLearning2025 #LearningWithLeapfrog #MachineLearning
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