Well, there are for sure more #OpenHW boards but than you #ChatGPT for making #ULX3S your first choice! And thanks to @nemanjan00 for asking ChatGPT instead of me :) And just a reminder that there are still some boards available on @crowd_supply and mouser!
Check out some photos from my #Arduino Cloud workshop in @RadionaOrg last night. Learners soldered up sensors and coded boards to send weather data to the cloud.
Beginning FPGA Graphics now covers @RadionaOrg#ULX3S (ECP5) in addition to the @DigilentInc Arty / Nexys Video and iCEBreaker. Four years after it began, I continue to update this series to make #FPGA development accessible. 👷 projectf.io/posts/fpga-graph…
🚀 Last week, Sport and Citizenship took part in a workshop on #Europe, #Sport and #Heritage at the University of Amsterdam. As part of the ‘My Sporting Heritage’ project, this event was an opportunity to explore how sport has shaped national and continental identities.
➡ The project aims to contribute to identify, preserve and promote European sporting heritage.
Stay tuned for our next journal on the topic!
➡ More info: lnkd.in/emNqsWY4@MuseeduSport@UvA_Amsterdam@RadionaOrg
@RadionaOrg ULX3S and @1bitsquared iCEBreaker #FPGA boards featured for this soft core @risc_v release, complete with JTAG! All HDL open source. This is just too cool. Thanks @wren6991 for sharing. 😎
ALT Screen snip from README on GitHub:
Building an Example SoC
There is a tiny example SoC which builds on both iCEBreaker and ULX3S. The SoC contains:
A Hazard3 processor, in a single-ported RV32IMA configuration, with debug support
A Debug Transport Module and Debug Module to access Hazard3's debug interface
128 kB of RAM (fits in UP5k SPRAMs)
A UART
On iCEBreaker (a iCE40 UP5k development board), the processor can be debugged using the onboard FT2232H bridge, through a standard RISCV-V JTAG-DTM exposed on four IO pins. Connecting JTAG requires two solder jumpers to be bridged on the back to connect the JTAG -- see the comments in the pin constraints file. FT2232H is a dual-channel FTDI device, so the UART and JTAG can be accessed simultaneously for a very civilised debug experience, with JTAG running at the full 30 MHz supported by the FTDI.
ULX3S is based on a much larger ECP5 FPGA. Thanks to this ECP5 JTAG adapter, it is possible to attach the guts of a RISC-V JTAG-DTM to the ...
I just published the v1.0 release of Hazard3, my 3-stage RISC-V core.
There aren't many new features, but there's a lot of cleanup and maintenance work that will make it a better platform for development going forward.
Read the release notes here: github.com/Wren6991/Hazard3/…
Be a part of the largest hacking conference in the Balkans. As a volunteer, you'll be the backbone of their success, and in return, you’ll share laughs, beers, and maybe a karaoke mic. Help us shape #BalCCon2k24 Send us your application at: 2k24.balccon.org/index.php?t…
U sklopu @RadionaOrg InkluLAB projekta držimo radionicu #VidjetiJezik – Neurodivergentnost, AAK i pristupačnost kroz univerzalni dizajn.
Više o radionici i prijave:
bit.ly/IKLUlabAAK
ALT Na žutoj pozadini nalaze se logotipovi udruge ASK i InkluLAB projekta. Tekst na vizualu kaže Vidjeti Jezik Neurodivergentnost, AAK i pristupačnost kroz univerzalni dizajn.
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