The irony: the entire #RISCV base ISA (RV64GC) is beautifully RISC: simple opcodes, fixed 32-bit instructions ( compressed), load/store architecture, no flags, no implicit state. Then RVV comes along and throws all those principles out the window: global implicit state, (1/5)

extremely complex "super-SIMD" that is difficult to efficiently map in a JIT. A more traditional SIMD extension with fixed vector widths and clearly defined instruction semantics would have been much more JIT-friendly. The upcoming P extension does go in that direction, (4/5)

A small rant about vector extensions in RISC-V, although I like RISC-V in general. But why is RISC-V's vector extension (RVV) so different from other SIMD instruction sets like x86's SSE/AVX or ARM's NEON? It seems like RVV is designed to be more flexible and scalable, (1/3)

but it also makes it more complex and harder to implement a JIT compiler for it in my PasRISCV emulator, where the JIted code needs often to bailout to the interpreter for non-native-SIMDizable code cases. I hope that the RISC-V foundation can come up with a more clean and (2/3)

Sometimes, even in technical discussions, you can present clear evidence, working examples, and credible sources, but before any real back-and-forth can even start, the only reply is a block. And I was ready to talk openly and willing to find common ground.

A pity, as I used to hold the one well known person in high regard, which makes it all the more disappointing now. It was about whether LLMs can count letters. I provided a working demo and peer-reviewed research showing it’s possible under the right setup, but the exchange ...