Last day of #RISCVSummit kicks off with really interesting talk by Tanya from @Ainekk0 , describing the role of AI agents and how @risc_v is an ideal substrate. Really exciting to hear that CORE-ET has been donated to @OpenHWFdn and made available open source

First keynote of #riscvsummit is @dadarstan giving a full roadmap of the bright Agentic silicon development future we are trying to build over at @AIFoundryorg and @OpenHWFdn

Rich Neale, my @EPCCed PhD student, has a poster today at #RISCVSummit exploring ET-SoC-1 for #hpc and exploring what the term "transputer" means wrt modern architectures. Thanks to @Ainekk0 for access to the hardware, some really interesting early performance PDE solver results

Grateful to take the stage tomorrow at @risc_v Summit Europe in Bologna, where I’ll speak about a vision that is still at an early stage, but worth pursuing. #Openarchitectures, #AIFactories, & a new capability path for small countries with bold talent. #RISCVSummit #Albania

Last year the @risc_v #HPC SIG published a gap analysis, with #lustre parallel file system a high priority. @Openchip_ picked this up and have done a fantastic job getting #riscv support upstreamed in #lustre. Really nice summary at #RISCVSummit, showcasing ecosystem progress

Really interesting talks by Yiftach from @NextSilicon about the Arbel @risc_v core and wider plan for large core count CPU at #RISCVSummit . He even had a physical Arbel-based CPU with him to show.

At the #RISCVsummit @LucaBeniniZhFe is giving a keynote on how the AI race us just beginning and what we can do going into detailed with closely coupled accelerators #RISCV @pulp_platform