A non-profit, global organisation where hardware and software designers collaborate in the development of open source cores, related IP, tools and software.
Today I am at @computextaipei at the #RISCV Day hold here, it us starting with @Andes_Tech Chairman Frankwwll Lin who is Aldo active in the RISC-V Alliance Taiwan
A new open source project has joined the OpenHW Foundation ecosystem!
Ainekkoโs CORE-ET Silicon Platform is now an OpenHW Foundation project, bringing an open platform for low-power AI inference at the edge.
Learn more: hubs.la/Q04k4PZY0#OpenHW#RISCV#AI#opensource
๐กIn our latest committer profile article, Jรฉrรดme Quevremont shares lessons from building and scaling the OpenHW CVA6 project, why collaboration matters in open source, and how community engagement drives innovation in open hardware.
๐ Read his story:
newsroom.eclipse.org/eclipseโฆ
WOHA, big NEWS!!! another, awesome open source Hardware RTL project released by @Ainekk0 at the #OpenHW repository! And it is Apache 2.0 with some NICE #RISCV cores inside......
Plus real chips will be made, check out more! Come and collaborate!
@FelixCLC_@rhatr
At @ocxconference one of the most compelling discussions around embedded systems focused on control. In this article, @Eff_Connected explores how RISC-V and @OpenHWFdn cores are giving manufacturers more flexibility to design around exact workloads.
๐ hubs.la/Q04gcnbQ0
๐ Meet Jรฉrรดme Quevremont, @EclipseFdn committer and contributor to OpenHW CVA6 and OpenHW CORE-V cores.
After 20 years in proprietary hardware development, he transitioned into the world of open source hardware and RISC-V.
Read about his journey:
hubs.la/Q04g5WDF0
WOHA, big NEWS!!! another, awesome open source Hardware RTL project released by @Ainekk0 at the #OpenHW repository! And it is Apache 2.0 with some NICE #RISCV cores inside......
Plus real chips will be made, check out more! Come and collaborate!
@FelixCLC_@rhatr
Tune in now for Advanced D&V flow using virtual prototype high-level synthesis for #RISC-V based SoC!
Explore early integration, continual validation, and optimization of RISC-V SoCs with virtual platforms and HLS.
Join #OpenHW here: hubs.la/Q047GhJ90
1 WEEK to go!
Donโt miss Advanced D&V flow using virtual prototype HLS for #RISC-V SoCs with #OpenHW Foundation, CircuitSutra & RISE-DA.
Learn how shift-left methods help catch architecture bottlenecks early and avoid costly re-spins.
Register here: hubs.la/Q046MSc50
Advanced D&V flow for RISC-V SoCs
Explore shift-left design with virtual platforms HLS and see RISE-DAโs Agentic AI Spec-to-Silicon flow for early HW/SW validation.
Register here ๐ hubs.la/Q046MTbL0#RISCV#HLS#SoCDesign
๐ฅ Embedded World 2026 is officially underway in Nuremberg!
Stop by the #EclipseFdn pavilion to explore open source innovation across embedded systems.
A big thank you to our sponsors for helping make our presence at Embedded World possible: @codethink, Eurotech, @OpenHWFdn, OpenVSX, #ThreadX, @SDVeclipse, ORC, @EclipseJavaIDE, @ECDTools and Theia AI.
๐ Meet the team at booth 4-554 in hall 4 and see live demos in action.
#embeddedworld#ew26#opensource