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Semiconductor Engineering @SemiEngineering
Joined September 2013
  • Tweets 7,070
  • Following 3,912
  • Followers 17,055
1,441 Photos and videos
Semiconductor Engineering retweeted
Semiconductor Engineering@SemiEngineering
Jun 11
Special Report Standalone GPUs are being replaced by heterogeneous SoCs and chiplets that combine CPUs, GPUs, and NPUs to eliminate memory bottlenecks, reduce latency, and boost efficiency. semiengineering.com/agentic-… #GPUs #CPUs #datacenters #NPUs #semiconductor #AgenticAI

Agentic AI Is Changing Data Center Architectures

Standalone GPUs are being replaced by heterogeneous SoCs and chiplets that combine CPUs, GPUs, and NPUs to eliminate memory bottlenecks, reduce latency, and boost efficiency.

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New technical papers recently added to Semiconductor Engineering’s library semiengineering.com/chip-ind… #semiconductor
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Latest: 14A PDKs; 2nm funding; memory deal; optimizing EUV output; auto chips report; HW security exploits; humanoids; H-1B policy; diamonds for heat; Europe’s IC progress; imec’s latest; AI for EDA ontology.. semiengineering.com/chip-ind… #semiconductor #EUV #cybersecurity @imec_int

Chip Industry Week In Review

14A accelerates; 2nm funding; memory deal; optimizing EUV output; KGD screening; McKinsey's auto chips report; HW security exploits; humanoids; H-1B policy; diamonds for heat; Europe's IC progress;...

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Scaling to tens of millions of CPO units per year requires the industry to first settle on automated, cost-effective methods for electrical and optical testing. semiengineering.com/co-packa… #CPO #datacenters #chiplets #photonics #semiconductor

Co-Packaged Optics Testing Faces Steep Data Center Ramp

Scaling to tens of millions of CPO units per year requires the industry to first settle on automated, cost-effective methods for electrical and optical testing.

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How agents can be used to divide and conquer IC design problems. semiengineering.com/building… #semiEDA #AgenticAI #semiconductor #multiagentsystems @AlphaDesignAI #LLMs #agentorchestration #chipdesign

Building Multi-Agent Systems For ASIC Flows

How agents can be used to divide and conquer IC design problems.

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Majority of AI initiatives falter; synthetic data gaining traction due to limited real-world data. semiengineering.com/ai-model… #semiconductor #AImodels #semiconductorinspection

AI Models Transform Defect Inspection And Review, But Can Fail To Scale

Majority of AI initiatives falter; synthetic data gaining traction due to limited real-world data.

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Semiconductor Engineering retweeted
Semiconductor Engineering@SemiEngineering
Jun 1
Special Report: Reducing variation in manufacturing, monitoring behavior over time, and targeting specific workloads can have a big impact on power, performance, and area/cost. semiengineering.com/the-sub-… #semiconductor #14A #1nm #CFETs #GAAFETs #2nm #highnaeuv #processvariation

The Sub-2nm Paradox

Reducing variation in manufacturing, monitoring behavior over time, and targeting specific workloads can have a big impact on power, performance, and area/cost.

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Semiconductor Engineering retweeted
Semiconductor Engineering@SemiEngineering
Jun 6
As threats evolve faster, protecting security algorithms from design through manufacturing and across the supply chain is becoming more difficult. semiengineering.com/keeping-… #cybersecurity #securityalgorithms #cryptography #PQC

Keeping Security Algorithms Current Is Getting Harder

As threats evolve faster, protecting security algorithms from design through manufacturing and across the supply chain is becoming more difficult.

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New research points to safer devices with less loss at low voltages, but problems remain for high-voltage industrial applications. semiengineering.com/gan-powe… #GaN #powerdevices #powersemiconductor

GaN Power Devices Power Up

New research points to safer devices with less loss at low voltages, but problems remain for high-voltage industrial applications.

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Semiconductor Engineering retweeted
Semiconductor Engineering@SemiEngineering
Jun 5
Latest: Computex shows AI ecosystem; fully autonomous chip design; Intel targets AI racks; Nikon’s 1.5 micron L/S litho; Apple’s chiplet era; 4.5K chips/AI server rack; HBM price hikes; SiC guidelines; MXenes; autonomous edge chiplets. semiengineering.com/chip-ind… #semiconductor

Chip Industry Week In Review

Computex shows AI ecosystem; fully autonomous chip design; Intel targets AI racks; Nikon's 1.5 micron L/S litho; IC market rises; Apple's chiplet era; 4,500 chips per AI server rack; HBM price hikes;...

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Satellite constellations with extra onboard compute are several steps away from handling full AI workloads for people on Earth. semiengineering.com/orbital-… #datacenters #ODCs #OrbitalDataCenters #radhard #liquidcooling #semiconductor

Orbital Data Centers Are Souped-Up Satellites – For Now

Satellite constellations with extra onboard compute are several steps away from handling full AI workloads for people on Earth.

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A look inside the next-generation AI server rack. youtu.be/6K7ZDX7kROQ?si=UfFY… #datacenters #AI #3DIC #1MWdatacenters #AIinference @Synopsys #Aitraining

1 Megawatt Racks In Data Centers

The demand for performance in an AI data center is causing a huge s...

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Multi-die assemblies give chip architects the option to change some dies while keeping the rest of the system intact, but which is best to keep? semiengineering.com/swapping… #chiplets #IO #inputoutput #semiconductor

Swapping Out Chiplets: I/Os Vs. Compute

Multi-die assemblies give chip architects the option to change some dies while keeping the rest of the system intact, but which is best to keep?

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Semiconductor Engineering retweeted
Semiconductor Engineering@SemiEngineering
May 26
Chiplets are notoriously expensive and finicky today, and they raise questions about how costs can be managed and reduced. If chiplets are to reach their full potential, those issues will need to be solved. semiengineering.com/with-chi… #chiplets #semiconductor

With Chiplets, What Role Does Economics Play?

Costs can rise with chiplets. Will that change? Will it matter?

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Semiconductor Engineering retweeted
Semiconductor Engineering@SemiEngineering
May 29
Latest: AI panel-level packaging innovations at ECTC; cool HBM; 2nm EDA tools; side-channel attacks in 2.5/3D; Huawei claims; IC talent initiative; glass core substrates; SiC; DRAM sizing; hybrid bonding ... semiengineering.com/chip-ind… #semiconductor #advancedpackaging #ECTC #HBM

Chip Industry Week In Review

AI panel-level packaging innovations at ECTC; cool HBM; 2nm EDA tools; side-channel attacks in 2.5/3D; Huawei claims; IC talent initiative; glass core substrates; memory test facility; Taiwan...

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Moving Defect Detection And Classification To The Edge: Explosion in defectivity requires much faster determination of critical and non-critical defects.semiengineering.com/moving-d… #2nm #semiconductor #edgecomputing #waferinspection

Moving Defect Detection And Classification To The Edge

Explosion in defectivity requires much faster determination of critical and non-critical defects.

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