May 7
PCIe 8.0规范草案0.5版正式进版：锁定1TB/s双向带宽，目标2028年正式推出
PCIe 8.0 Specification Draft Version 0.5 Officially Enters Review: Targeting 1TB/s Bidirectional Bandwidth, Formal Release Planned for 2028
PCI-SIG在美国年度开发者大会（DevCon 2026）上宣布，PCI Express 8.0规范草案0.5版已正式向会员发布，标志着首个完整草案提前完成。该标准仍计划于2028年正式推出，在x16配置下可提供高达256 GT/s的原始传输速率和高达1.0 TB/s的双向带宽。
从草案0.3到0.5，首个完整草案锚定关键技术路线
草案0.5整合了各成员对2025年9月发布的0.3版草案的反馈意见，是首个涵盖电气、逻辑、合规及软件全部架构层面的完整规范版本。PCI-SIG总裁兼主席Al Yanes表示，0.5版草案的发布时间较前几代标准略有提前，技术工作组正在全力以赴推进制定工作。
核心目标已明确锁定：PCIe 8.0将延续PAM4信令和FLIT编码技术路线，在保持向后兼容性的同时，将PCIe 7.0的128 GT/s速率翻倍至256 GT/s。这意味着，即使是最小的x4链路也能达到256 GB/s带宽，足以驱动未来的加速器、智能网卡（NIC）、固态硬盘以及与CXL紧密耦合的平台设计。
铜缆逼近物理极限，光学与新型连接器提前卡位
随着信号速率推升至256 GT/s，传统铜基物理层正面临前所未有的挑战。插损预算、串扰及反射效应在PCIe 5.0与6.0时代已构成严重制约，而在PCIe 8.0世代，这些限制将急剧放大。现有边缘连接器和主板走线方式可能无法在合理的功耗（均衡）或延迟（FEC）代价下，维持满足要求的信号完整性。
为此，PCI-SIG正积极评估新型连接器技术，工作小组在维持兼容性前提下，将减少连接器接脚数列为重点目标之一。Yanes更指出，线缆方案的创新很可能成为PCIe 8.0的“重头戏”。
光学互连同样加速步入标准化快车道。PCI-SIG已于2025年6月发布光学感知重定时器工程变更通知，兼容PCIe 6.0与7.0设计，并已规划纳入PCIe 8.0标准体系。这使PCIe架构具备跨越机架与Pod实现远距离互连的能力，正契合AI训练集群对跨节点高速通信的刚需。
产业提前卡位：AI工作负载驱动，头部玩家密集布局
尽管最终规范尚在制定中，产业链上下游已明显提前卡位。Marvell在2月份的DesignCon 2026上展示了PCIe 8.0 SerDes，以256 GT/s的数据速率运行，结合其收购的Celestial AI光互连业务，瞄准的是2030年预计将达100亿美元的光互连市场。
博通同样在SC25上公布了PCIe交换芯片路线图：计划2027年推出适用于PCIe 7.0的91000系列交换芯片，2028年将推出92000系列PCIe 8.0 Switch。
Synopsys也在DesignCon 2026上展示了被其称为“PCIe 8.0级电气性能”的256 GT/s链路演示，包括眼图分析及接收端性能验证。
从应用驱动力看，AI DC对Scale-up架构的需求被普遍视为推动PCIe规范快速迭代的动力。GPU与加速器之间的数据交换频率与规模远超以往，使系统对内部互连带宽的要求持续攀升。PCIe正在从传统的主板级I/O总线，逐步演变为数据中心内部互连的中枢架构。
与此同时，CXL协议构建在PCIe物理层之上，随着CXL 3.1支持基于端口的路由和多层交换，其互连范围已能从机架内扩展到整个数据中心，实现数千节点共享同一内存池的池化能力，PCIe 8.0所提供的超大规模I/O带宽，将直接推动CXL架构向更深层次的内存与加速器解耦演进。
The #PCIe 8.0 specification, draft 0.5 is now available for member review. This marks the official first draft of the specification, and it remains on track for full release to #PCISIG members by 2028.
To learn more about the latest PCIe specification release and the feature objectives, read the blog > bit.ly/4tjvD8o
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DesignCon 2026 made it clear: 200G per channel is the new baseline and linear interconnects are surging. Semtech highlights: Best Paper finalist with @TEConnectivity, and leading the industry shift to redrivers: hubs.la/Q048yCWg0
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Design is not just what you see, it’s how it works, and today, our graduates are ready to show the world what they’ve built.
From learning the fundamentals to creating impactful, real-world solutions, this moment marks the transformation of our learners into confident, industry-ready designers.
Join us at Design Con as we celebrate their creativity, growth, resilience, and excellence at the graduation .
#Utiva #DesignCon #UtivaGraduation2026 #ProductDesign #TechInAfrica #DigitalSkills #DesignCommunity #FutureDesigners #GraduationDay #Creatives
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Mar 20
DesignCon Breaks Records in 2026 hubs.li/Q0469T170 #DesignCon2026 #DesignConRecords #ChipDesign #SemiconductorEvents #tradeshowexhibits #tradeshows #ttnmgblog
Mar 19
[ADVANS Group at DesignCon 2026 — Thank you!]
DesignCon 2026 wrapped up a few weeks ago, and we’d like to thank everyone who stopped by Booth 204 during the event.
📸 Last day at the show. Tony made a new friend.
#DesignCon #DesignCon2026
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Mar 19
Clarity ACEで“配線抽出の手作業”をゼロへ✨
マルチチャネルEM解析では、抽出作業がフロー全体の負荷になりがちです。
Clarity ACE（Automated Channel Extraction）は、この工程を自動化し、
DDR5 / 224G SerDes / チップレット / SI/PI / 熱などの検証をよりスムーズに進められるようにします。
抽出に時間を取られず、設計へまっすぐ集中できる環境へ。
DesignConの見どころはこちら（英語)👇
🔗community.cadence.com/cadenc…
#EM解析 #シグナルインテグリティ #PI解析 #SerDes #DDR5 #高速I_O
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Mar 18
From #DesignCon 2026. Navneet Kataria is demonstrating 448 Gbps per Lane in Action with #Foxconn and #PAM6 technology, along with demonstrating backplane cable testing with a #ShockLine 4-port VNA using 32 channels with a scalable RF switch matrix and #SamTec interfaces.
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Mar 17
At DesignCon ev eryone asks“What’s new?” From the portable MHO900 (800 MHz) up to the DS80000 (13 GHz) oscilloscope on the bench. But the quiet surprise for a lot of visitors? RSA6000 spectrum analyzer the new DNA5000/6000 VNAs.
youtu.be/SezA_2NfSLI
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Mar 17
In this video from the #DesignCon show floor, #Anritsu's Hiroshi Goto demonstrates a live #PCIe6 TX/RX validation workflow using the MP1900 platform: bit.ly/3Pfpko3
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DesignCon 2026 | Specifying for Harsh Environments | PCIe 7.0 & 8.0 | LVDS Connectors | Waterproof & Hermetic Products - mailchi.mp/connectorsupplier…
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Mar 16
Steve Hillerich, new product development manager for #Molex, showed us at #DesignCon the new Impress Co-Packaged Copper solution for data centers and AI workflows. Watch the video to see how the interconnect compression attaches to the substrate. #DataCenterDesign
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Mar 15
Discover 3M solutions advancing high‑density computing. Meet us at DesignCon, booth 420. bit.ly/4lxxuEm
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Andy’s back from the 2026 Analog Aficionados meetup, held at #DesignCon this year, and pieces together some history of the event as well as launching a downloadable annual calendar commemorating the event. bit.ly/4bmlG2V
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Mar 14
At DesignCon 2026, Sonam Sadhukhan was honored in the 40 Under 40 program and selected as one of the top six speakers.
The recognition highlights her contributions as a senior staff engineer on Marvell’s Optical PHY team, where she is helping build high‑speed infrastructure for the AI data center era. The article also reflects on her prior work in automotive SerDes and clocking architectures, as well as her commitment to mentoring and supporting underrepresented engineering talent.
Read to learn more about Sonam’s work and leadership: mrvl.co/4bGhmgk
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#QuantumComputing is redefining what’s possible.🚀
Dive into the fundamentals and future trends with #Rosenberger North America’s latest presentation from #DesignCon 2026!🌐💻
Watch here: youtu.be/k0_kX7WgpDU
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