PCIe 8.0规范草案0.5版正式进版：锁定1TB/s双向带宽，目标2028年正式推出 PCIe 8.0 Specification Draft Version 0.5 Officially Enters Review: Targeting 1TB/s Bidirectional Bandwidth, Formal Release Planned for 2028 PCI-SIG在美国年度开发者大会（DevCon 2026）上宣布，PCI Express 8.0规范草案0.5版已正式向会员发布，标志着首个完整草案提前完成。该标准仍计划于2028年正式推出，在x16配置下可提供高达256 GT/s的原始传输速率和高达1.0 TB/s的双向带宽。 从草案0.3到0.5，首个完整草案锚定关键技术路线 草案0.5整合了各成员对2025年9月发布的0.3版草案的反馈意见，是首个涵盖电气、逻辑、合规及软件全部架构层面的完整规范版本。PCI-SIG总裁兼主席Al Yanes表示，0.5版草案的发布时间较前几代标准略有提前，技术工作组正在全力以赴推进制定工作。 核心目标已明确锁定：PCIe 8.0将延续PAM4信令和FLIT编码技术路线，在保持向后兼容性的同时，将PCIe 7.0的128 GT/s速率翻倍至256 GT/s。这意味着，即使是最小的x4链路也能达到256 GB/s带宽，足以驱动未来的加速器、智能网卡（NIC）、固态硬盘以及与CXL紧密耦合的平台设计。 铜缆逼近物理极限，光学与新型连接器提前卡位 随着信号速率推升至256 GT/s，传统铜基物理层正面临前所未有的挑战。插损预算、串扰及反射效应在PCIe 5.0与6.0时代已构成严重制约，而在PCIe 8.0世代，这些限制将急剧放大。现有边缘连接器和主板走线方式可能无法在合理的功耗（均衡）或延迟（FEC）代价下，维持满足要求的信号完整性。 为此，PCI-SIG正积极评估新型连接器技术，工作小组在维持兼容性前提下，将减少连接器接脚数列为重点目标之一。Yanes更指出，线缆方案的创新很可能成为PCIe 8.0的“重头戏”。 光学互连同样加速步入标准化快车道。PCI-SIG已于2025年6月发布光学感知重定时器工程变更通知，兼容PCIe 6.0与7.0设计，并已规划纳入PCIe 8.0标准体系。这使PCIe架构具备跨越机架与Pod实现远距离互连的能力，正契合AI训练集群对跨节点高速通信的刚需。 产业提前卡位：AI工作负载驱动，头部玩家密集布局 尽管最终规范尚在制定中，产业链上下游已明显提前卡位。Marvell在2月份的DesignCon 2026上展示了PCIe 8.0 SerDes，以256 GT/s的数据速率运行，结合其收购的Celestial AI光互连业务，瞄准的是2030年预计将达100亿美元的光互连市场。 博通同样在SC25上公布了PCIe交换芯片路线图：计划2027年推出适用于PCIe 7.0的91000系列交换芯片，2028年将推出92000系列PCIe 8.0 Switch。 Synopsys也在DesignCon 2026上展示了被其称为“PCIe 8.0级电气性能”的256 GT/s链路演示，包括眼图分析及接收端性能验证。 从应用驱动力看，AI DC对Scale-up架构的需求被普遍视为推动PCIe规范快速迭代的动力。GPU与加速器之间的数据交换频率与规模远超以往，使系统对内部互连带宽的要求持续攀升。PCIe正在从传统的主板级I/O总线，逐步演变为数据中心内部互连的中枢架构。 与此同时，CXL协议构建在PCIe物理层之上，随着CXL 3.1支持基于端口的路由和多层交换，其互连范围已能从机架内扩展到整个数据中心，实现数千节点共享同一内存池的池化能力，PCIe 8.0所提供的超大规模I/O带宽，将直接推动CXL架构向更深层次的内存与加速器解耦演进。

From #DesignCon 2026. Navneet Kataria is demonstrating 448 Gbps per Lane in Action with #Foxconn and #PAM6 technology, along with demonstrating backplane cable testing with a #ShockLine 4-port VNA using 32 channels with a scalable RF switch matrix and #SamTec interfaces.

In this video from the #DesignCon show floor, #Anritsu's Hiroshi Goto demonstrates a live #PCIe6 TX/RX validation workflow using the MP1900 platform: bit.ly/3Pfpko3

Discover 3M solutions advancing high‑density computing. Meet us at DesignCon, booth 420. bit.ly/4lxxuEm

At DesignCon 2026, Sonam Sadhukhan was honored in the 40 Under 40 program and selected as one of the top six speakers. The recognition highlights her contributions as a senior staff engineer on Marvell’s Optical PHY team, where she is helping build high‑speed infrastructure for the AI data center era. The article also reflects on her prior work in automotive SerDes and clocking architectures, as well as her commitment to mentoring and supporting underrepresented engineering talent. Read to learn more about Sonam’s work and leadership: mrvl.co/4bGhmgk

Marvell demonstrated new advances in active electrical cable technology at DesignCon 2026.   In this video, Michael Arsenault highlights a live demo of the Golden Cable running on the first‑to‑market 224G Alaska A 1.6T DSP. The setup showcases a clean 3‑meter, 30‑gauge channel with a 10⁻¹⁰ pre‑FEC BER, along with validation that the same DSP can extend performance out to 6.5 meters.

Thank you for visiting us at #DesignCon 2026, where we showcased innovations in high-speed Ethernet and AI fabric test, coherent optics, fiber and photonic manufacturing test, and PCIe/protocol analysis. Watch the highlights reel from the show floor: viavisolutions.com/en-us/pro…

Marvell demonstrated its 200G/lane active copper cable technology for AI scale‑up and in‑rack connectivity at DesignCon 2026. In this video, Nicola Bramante showcases 200G/lane active copper cable technology in AI scale up and in rack connectivity. ACC is a technology that is an emerging alternative to pure copper cables; it allows for lower power, lower latency and lost cost. explains how Marvell ACC solutions deliver longer reach, thinner cables and lower power compared to traditional copper, enabled by advanced analog equalization that exceeds competitive approaches. The demo features a 1.6T, two‑meter cable connected to a SerDes system emulating in‑rack traffic, with measured bit error rates between e‑8 and e‑9 across all lanes. Marvell is excited to have its ACC as an addition to the company's AI scale up portfolio, which already includes PCIe, AEC, and AOC.

At DesignCon 2026, Marvell showcased a live demonstration of its Alaska P PCIe retimers. In this video, Anushree Jumade walks through how these low‑power, low‑latency retimers built on 5nm SerDes IP enable high‑speed server connectivity, with support for PCIe 6.0, CXL 3.x and up to 40 dB insertion loss compensation. The product comes in two variants, 16 lane and eight lane, which can enable high speed communication between different components in servers. The demo highlights a 7‑meter active electrical cable powered by Alaska P retimers, delivering a x16 Gen 6 link at 64 GT/s per lane. Alaska retimers are PCIe 6 compliant and support CXL 3.x, which makes them excellent solutions for XPU scale up and emerging aggregate systems.

At DesignCon 2026, Marvell introduced PCIe 8.0 SerDes delivering up to one terabyte per second of bidirectional bandwidth for next‑generation AI interconnects. In this video, Desh Mirle Jayaprakash highlights a demo with TE Connectivity that showcases ultra‑low jitter, robust equalization and best‑in‑class bit error performance under real system conditions. The demonstration enables customers and ecosystem partners to begin pathfinding new architectures for fastest CPU to CPU communication, GPU to GPU communication and high‑bandwidth links across CPUs, GPUs, NICs and DPUs. As AI servers and systems scale to hundreds of accelerators, PCI becomes the backbone of communication, and Marvell is leading the industry toward the PCIe 8 era.

Marvell had a strong presence at DesignCon 2026. Across the conference, Marvell experts shared insights on high‑speed interconnects, advanced packaging, photonic links, bi‑directional die‑to‑die interfaces and next‑generation switch architectures. At the Marvell booth, teams demonstrated key technologies spanning SerDes, active copper and electrical cables, and high‑bandwidth die‑to‑die connectivity. It was a great opportunity to meet engineers, connect with ecosystem partners and highlight the innovations that will shape future AI infrastructure.

I posted about co-packaged copper (CPC) last month while looking through the DesignCon materials. The debate about CPO versus copper rages on.

先週、『DesignCon 2026』が無事閉幕いたしました！ 初日の反響を受けて2日目はブースのレイアウトを変更するなど、スタッフ一同の創意工夫によって、より充実したブース運営となったようです😌 ▼KEL USA, Inc. のLinkedInでも、DesignCon 2026の様子をご紹介しています💻 linkedin.com/company/kelusa/

Discover the future of photonics and cable testing with the Santec at DesignCon 2026! Where:  Santa Clara Convention Center Santa Clara, CA Booth: 609 When: February 24-26, 2026 Come see the game-changer you’ve been waiting for and revolutionize your cable testing!

🎊 What an amazing time at #DesignCon this week! 🎉 We'd like to give a huge shoutout to our friends at @Tektronix, @TeledyneLecroy, and SiPhx for collaborating with us on some exciting demos, as well as everyone who visited us at our booth.

『DesignCon 2026』の出展報告です！ KEL USA, Inc. のブースでは、高速伝送コネクタやフローティングコネクタを中心に製品をご紹介しています。 日本からも営業・技術スタッフが足を運び、北米市場での認知拡大に向けて、ケルブランドのPR活動に取り組んでいます😀 当日のブースの様子を写真でもお届けします📷

#Designcon day 2.. If you’re here come by booth 529 if you want to talk PCB/PCBA mfg.

Scalable, Automated Signal Integrity Testing for High-speed Interconnects Come see us at DesignCon 2026 booth #1143

Today during #DesignCon, #Anritsu's experts will lead a series of technical sessions in the Great American Ballroom on design and test challenges associated with emerging high-speed chipsets, components, boards, and systems. See the full schedule: bit.ly/4u1S6Zm