Built a 2:1 multiplexer using gate-level Verilog modeling. Simple yet fundamental selecting between two inputs with basic logic gates. Every complex chip starts with mastering these building blocks! #NativesPlug #LearnInPublic #LOCUS2026 #15DayChallenge #NepalTech #LearnAndWin

15 days Daily learning One post a day 📚 Learn something new ✍️ Share what you learned 🌍 Post on LinkedIn, Twitter, or Facebook No perfection. Just consistency. Progress beats silence. #NativesPlug #LearnInPublic #LOCUS2026 #15DayChallenge #NepalTech #LearnAndWin