Netherlands' BESI: Samsung's Hybrid Bonding Adoption Decision Coming Soon Samsung Electronics is expected to introduce hybrid bonding technology — projected to be at the heart of next-generation semiconductor production — around the middle of this year. Dutch back-end equipment company BE Semiconductor Industries (BESI) stated during its Q1 earnings conference call on April 23 that "we should see more definitive news around the middle of this year regarding Samsung Electronics' (hybrid bonder adoption)." This is largely consistent with the outlook shared during the Q4/full-year 2025 earnings call in February, which indicated Samsung would adopt hybrid bonding in Q2. Unlike conventional thermo-compression (TC) bonding, hybrid bonding does not use fine metal bumps to connect stacked semiconductor dies. Instead, it is an advanced packaging technology that directly connects the copper (Cu) surfaces of two chips. When applied to High Bandwidth Memory (HBM) and new high-layer-count NAND flash, it can deliver performance improvements, reduced power consumption, and cost savings — because the direct copper-to-copper connection enables higher integration density and shorter interconnect lengths. That said, some observers suggest that hybrid bonding adoption could be delayed as the Joint Electron Device Engineering Council (JEDEC) moves to relax packaging height limits for next-generation HBM. On this point, BESI CEO Richard Blickman explained, "The only reason (JEDEC) is looking to relax HBM thickness specifications is because one of the three memory companies needs that height for its process," adding that "the other two are not affected by this change." The major HBM players are Samsung Electronics, SK Hynix, and Micron. The implication is that two of these three are pursuing hybrid bonding adoption for reasons beyond height considerations. Hybrid bonding produces chip-to-chip gaps of around 7 micrometers (㎛), which makes it advantageous for reducing the total thickness (height) of HBM packages. JEDEC is reportedly considering raising the height limit from the current 775㎛ to either 825㎛ or 900㎛. Analysts argue that if the package height limit is relaxed, the lifespan of existing TC bonding technology would be extended, while the introduction of hybrid bonding could be delayed — since hybrid bonding would no longer be required simply to reduce thickness. Blickman emphasized, "The advantages of hybrid bonding over conventional TC bonding — faster circuit speeds, lower power consumption, and reduced heat — are being increasingly clearly demonstrated," and "as Samsung Electronics has publicly disclosed, because of these technical benefits, (the relaxation of HBM thickness limits) has not changed the pace or rate of hybrid bonding adoption." Samsung Electronics introduced its hybrid bonding technology for HBM at NVIDIA's annual developer conference, GTC 2026, last March. At the time, Samsung stated that hybrid bonding improves thermal resistance by more than 20% versus TC bonding and supports 16-high and higher stacks. Interconnect density is also higher. According to BESI, hybrid copper bonding (HCB) offers 15× the interconnect density of TC bonding and more than 100× the energy-efficiency performance (EEP). BESI expects mass production of hybrid-bonding-based HBM to begin next year. Blickman explained, "All three manufacturers are conducting equipment evaluations against the same criteria set by a specific end customer," and "that end customer has asked the memory makers to secure hybrid-bonded stacked products by the end of this year, with the goal of bringing finished products to market next year." The end customer in question is most likely NVIDIA. BESI is regarded as the global leader in the hybrid bonding equipment market. It holds a technological edge in both precision and throughput, particularly in die bonding equipment. Applied Materials, the world's largest semiconductor equipment company, holds a 9% stake, making it BESI's largest shareholder.

Nvidia $NVDA CEO Jensen Huang just said we are at the beginning of a new market CPUs FOR AGENTS Here's who is already signed up to use Nvidia's new Vera CPU: EARLY ADOPTERS: - OpenAI - Anthropic - SpaceX $SPCX CLOUD PARTNERS: - Nebius $NBIS - Oracle Cloud $ORCL - CoreWeave $CRWV - Nscale - Crusoe - Firmus - Lambda - Together AI ECOSYSTEM PARTNERS: - Dell Technologies $DELL - HPE $HPE - Lenovo - Super Micro Computer $SMCI - Aivres - ASRock Rack - Asus - Compal - Foxconn - Gigabyte - Hyve Solutions - Inventec - Mitac Computing - MSI - Pegatron - QCT - Wistron - Wiwynn

JPMorgan Reiterates Overweight Rating on $MRVL, Maintains PT at $130 Analyst comments: "Marvell is set to report earnings Thursday, and we expect a continued volume ramp of its two large AI ASIC programs (Amazon Trainium 2 ASIC/Google Axion ARM CPU), strong demand for its 800G products, and the initial ramp of 1.6T optical DSPs. This is combined with a continued cyclical recovery in its enterprise and carrier segments. Overall, we expect April-quarter results (we estimate $1.875 billion, up 3% quarter-over-quarter) and July-quarter guidance (we expect $2.00 billion , up 7% quarter-over-quarter) to be in line with JPMorgan and consensus estimates, with solid datacenter growth led by its AI ASIC ramps, growth in 800G/1.6T AI optical shipments, 400ZR shipments, and HDD/SSD controllers. The remainder of its business should also show sequential growth driven by cyclical improvements and new product cycles. Recall that the team reaffirmed its April-quarter revenue outlook in early May. Since then, we believe accelerated compute demand remains strong, as indicated during earnings season from cloud and hyperscaler capex spending and AI infrastructure beneficiaries (e.g., MTSI, ALAB). On custom ASICs, the team continues its production ramp at Amazon with the Trainium 2 AI XPU ASIC, and as we recently highlighted, we believe Marvell’s Trainium 3 (3nm) program at AWS is progressing well and is on track to ramp in calendar year 2026 in high volumes. We also believe Marvell’s Microsoft AI ASIC MAIA Gen 2 (3nm) program is on track for a CY26 ramp, and Marvell has already won the Gen 3 MAIA (2nm/3nm chiplet – 3DSOIC) program, with production planned for a CY27/28 ramp. Within the optical business, 800G PAM4 optical DSP orders and shipments remain solid, with an increasing ramp of next-gen 1.6T DSP into the second half of the year. Overall, we estimate the team will drive $4 billion in total AI ASICs and networking revenues this year. In the cyclical business, demand from enterprise networking (Cisco) remains healthy, and demand in carrier infrastructure is stabilizing. In automotive, the divestiture of the auto business, expected to close in CY25 ($225–$250 million revenue in FY26), is a revenue headwind but should be accretive to earnings by $0.05–$0.10, assuming proceeds are used for share repurchases. More importantly, we see the team’s custom datacenter and AI ASIC pipeline continuing to expand (SmartNIC/DPU ASIC chips, HBM4 base die controller ASICs, eSSD controller ASICs, follow-on AI accelerator ASIC wins). We maintain our Overweight rating, as we see the team’s AI ASIC, optical, cloud, and storage segments continuing to drive solid growth while cyclical 5G and enterprise businesses recover." Analyst: Harlan Sur

XIAOMI CEO WARNS SMARTPHONE PRICES WILL KEEP RISING Lei Jun says smartphone prices are likely to climb over the next two years as memory chip costs rise. The pressure is coming from AI data-center demand pulling supply toward higher-margin memory products. TrendForce says conventional DRAM contract prices rose 90%-95% QoQ in Q1 2026. NAND flash prices rose 55%-60% in the same period. Xiaomi already raised prices on several handset models earlier this year by about $29. The AI memory shortage is no longer just a data-center problem. It is starting to show up in phones, PCs, consoles and other consumer electronics.

Too many people have been asking me why TTMI is up in pre-market, so I’ll answer it this one time. Next time, please look it up yourselves. PCB stocks surged sharply in the Chinese market today. The reason PCB names rallied in China is that Morgan Stanley analyzed NVIDIA’s next-generation Rubin rack and found that the rack ASP could reach roughly $7.8 million, almost doubling from GB300. More importantly, Morgan Stanley argued that this value uplift does not mainly come from the GPU itself, but from components such as PCBs ( 233%), MLCCs ( 182%), and ABF substrates ( 82%), which are expected to be the biggest beneficiaries. As a result, several PCB supply-chain names rallied sharply, including: Ding Tai Gao Ke (301377.SZ): 20%, limit-up The global No. 1 player in micro-drills and routers used in the drilling process, a critical step in PCB manufacturing. Shenghong Technology (300476.SZ): 13.3% and other PCB supply-chain companies.

APPLE AND INTEL REACH PRELIMINARY CHIP-MAKING AGREEMENT WSJ reports $AAPL and $INTC have reached a preliminary agreement for Intel to manufacture some chips for Apple devices. It is still unclear which Apple products Intel would make chips for. The Trump administration reportedly pushed for the deal, with Commerce Secretary Howard Lutnick meeting Apple, Nvidia, Musk, and others to bring them into Intel’s ecosystem. Intel now has partnerships with Apple, Nvidia, and Musk-linked companies. Washington is trying to turn Intel Foundry into a U.S. chipmaking platform for America’s biggest tech companies.

$DELL delivered the world’s first $NVDA Vera Rubin NVL72 rack to $CRWV marking the first confirmed shipment of Nvidia’s next-gen AI rack system. The system includes 72 Rubin GPUs, 36 Vera CPUs, 3.6 exaFLOPS of FP4 inference, 75TB of fast memory and 260TB/s of NVLink bandwidth.

"The companies are negotiating an agreement for $AVGO to finance the first phase of chip production, which would consume 1.3 GW of data center capacity and would cost around $18B. At that rate, the full 10 GW program, code-named Nexus, could cost $180B in chip production alone before factoring in data center construction and other costs."