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CCIX Consortium @CCIXConsortium

Developing the industry standard specification to enable coherent interconnect technologies between general-purpose processors and acceleration devices. #CCIX

Joined February 2018
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Our #CCIX webinar series provides an overview of the CCIX protocol, architecture model, agent types and more. Watch now: bit.ly/3zScsqG @XilinxInc @Arm

Webinar - CCIX Architecture Framework and Coherency Protocol

The first in the series of webinars for CCIX Consortium members, th...

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The #CCIX Software Developer’s Guide encourages development of a CCIX-based heterogenous system. Download the free guide today for an informative reference material for software-enablement of CCIX: bit.ly/2ZZFkxN
#CCIX technology results in significant improvements for low-latency applications by allowing the Home Agent (HA) to be placed closer to the memory. Read the CCIX blog to learn more about CCIX device configuration: bit.ly/2N5lyKM
#CCIX offers key benefits for high-performance applications such as machine learning (#ML), network processing, storage off-load and in-memory database. Find out how CCIX enables hardware accelerators to use shared memory in a cache coherent manner: bit.ly/2RJdSjN
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Dealing with increased data volumes requires an understanding of architectures, the flow of data between memory and processors, bandwidth, cache coherency and new interfaces. Learn how the #CCIX interface improves performance: bit.ly/2QaiqSm @SemiEngineering @synopsys
#CCIX is an open industry standard that supports #cachecoherency and memory expansion for processors and acceleration devices. Learn more: bit.ly/3ylmXlB
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Technologies such as #AI, #ML and #5G are changing the way data processing happens, resulting in new demand for #HPC performance enhancements. #CCIX addresses the need for faster data processing by enabling seamless chip-to-chip communication. Learn more: bit.ly/2MHzVo3
How can Redis benefit from #CCIX? In this demo, @Arm and @XilinxInc showcase the acceleration of #RedisEdge with CCIX, using the Arm Neoverse N1 System Development Platform with the Xilinx Alveo U280 Data Center Accelerator card. Watch now: bit.ly/3iYPs4q
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Interested in the advantages that #CCIX acceleration delivers to in-memory applications like Redis? Watch this full demo of the @Arm #Neoverse N1 System Development Platform and @Xilinx Alveo U280 Data Center Accelerator Card: bit.ly/3iYPs4q bit.ly/37EEDfe
Learn more about the changes coming to the #CCIX specification to and support the wide variety of packaging technology that is out there on the market today. bit.ly/3hl58OL
The memory expansion capability enabled by #CCIX allows Storage Class memory (SCM) to have a significantly lower cost solution with much larger storage capacity. Design your #accelerator using CCIX software: bit.ly/2UP1fV2
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The CCIX Consortium continues to work on reducing latency for accelerators and interconnect use cases. From die-to-die integration or layered architecture, #CCIX is continuing to evolve the specification to support a wide variety of packaging technology. bit.ly/3hl58OL
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Learn how the #CCIX Acceleration Function (AF) works and the various components that comprise the CCIX AF to greatly reduces the software development burden through the use of Acceleration Function components: bit.ly/2MGW327
As the industry looks to move from the standard packet interface on PCIe to a #FLIT format #CCIX 2.0 is optimizing for latency and still ensuring compatibility with PCIe Gen 6. Learn more at bit.ly/3hl58OL
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The #CCIX specification ensures that processors using different instruction set architectures can coherently share data with accelerators such as #GPUs, #FPGAs, and Smart Network Accelerators. Become a CCIX member and design your products with CCIX: bit.ly/3kk9KUk
The #CCIX Software Developer’s Guide describes CCIX software architecture and provides guidelines for software developers to implement, configure and manage CCIX based systems. Download the guide today: bit.ly/3h9cQst
Learn how the @Cadence #CCIX verification tool set helps speed up the verification process for a variety of CCIX topologies. bit.ly/3vUqcjc via @chipestimate
The #CCIX specification is available to members for system designers to begin implementing CCIX #cachecoherent technology and lower #latency TODAY. Anyone can become a CCIX consortium member, find out how: bit.ly/2RZmYsl
#CCIX 2.0 is focused on latency through a transport agnostic interface and reducing the overhead with a new CCIX FLIT. Learn more at bit.ly/3hl58OL
From its origin, #CCIX has been designed to be portable and. Learn more about how CCIX’s layered architecture design makes it flexible to take advantage of new transports that that are coming on the market. bit.ly/3hl58OL
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