#ICYMI you can now access the posters from #Spring2022RISCVWeek. The posters covered a range of topics from FPGA platforms to ML to vectors and more. View them all here: hubs.la/Q01b1Kfc0
At #Spring2022RISCVWeek, SiFive’s Perrine Peresse highlighted the benefits the #RISCV IOMMU specification will provide for virtualized systems. Stay tuned for the video! #NoLimits
“RISC-V empowers our community to seize growing opportunities.” At #Spring2022RISCVWeek, #RISCV CEO @Calista_Redmond discussed how RISC-V is enabling innovation across industries, including automotive, consumer IoT devices, AI/ML, edge computing, and HPC. #RISCVEverywhere
Together with my poster (@UNIMORE_univ@pulp_platform) at the #Spring2022RISCVWeek in #Paris! What an event! Many great people and exciting news from industry and academia have made this event a global success. No doubts: @risc_v is an inspiring and vibrant community to be in!
Interested in graph analytics on #RISCV GPU? Curious about using the TUM Uncore environment for RISC-V for teaching, #AI and quantum computing? Join our second poster session and exhibition to learn all this and more. #Spring2022RISCVWeek
At 10 a.m. CEST (1 a.m. PT), #RISCV'S @mark_riscv and @VRULLEU's Philipp Tomsich will provide an overview of existing software and ongoing initiatives to enable adoption of RISC-V for ISVs, software distributions and system vendors. hubs.la/Q019wkgK0#Spring2022RISCVWeek
Join @VRULLEU founder Philipp Tomsich at 9:40 a.m. CEST (12:40 a.m. PT) for a presentation on key initiatives to create a robust ecosystem for ISVs while unlocking the benefits of #RISCV’s mix-and-match approach to ISA customization: hubs.la/Q019wm900#Spring2022RISCVWeek
Happy #RISCV International Day! It's the final day of #Spring2022RISCVWeek. We are kicking things off at 9 a.m. CEST (12 a.m. PT) with an exciting State of the Union address from #RISCV CTO @mark_riscv. Come hear about RISC-V's achievements and plans: hubs.la/Q019wklj0
“In a world where Dennard scaling & Moore's law is ending, you need to use architectural innovation to succeed”.
Zdeněk Přikryl presented at #Spring2022RISCVWeek@risc_v
Download our latest whitepaper to learn how processor design is being redefined my.mtr.cool/zfuicmtqzs
Day 2 of #Spring2022RISCVWeek has come to a close! Thank you to everyone for making it such an eventful day. We are excited to see everyone tomorrow for "RISC-V International Day" and the final day of our 3-day event.
Curious about exploring #RISCV high performance compute clusters? Interested in hearing about composable custom extensions and function units for RISC-V? Come by the second #Spring2022RISCVWeek poster session to learn all this and more.
#NaxRiscv is a recently developed OoO RV32/64 IMACSU softcore intended to provide better single threaded performances, keep logic resources usage reasonable, and more. Join @dolu1990 at 2:10 p.m. CEST (5:10 a.m. PT) to learn more. hubs.la/Q019hpQh0#Spring2022RISCVWeek
Several EPI partners are participating at the #Spring2022RISCVWeek in Paris! 🥳
Francesco Minervini from @BSC_CNS is presenting Vitruvius, the Vector Processing Unit powering the Vector EPI Accelerator. 💪