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#ICYMI you can now access the posters from #Spring2022RISCVWeek. The posters covered a range of topics from FPGA platforms to ML to vectors and more. View them all here: hubs.la/Q01b1Kfc0
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11 May 2022
At #Spring2022RISCVWeek, SiFive’s Perrine Peresse highlighted the benefits the #RISCV IOMMU specification will provide for virtualized systems. Stay tuned for the video! #NoLimits

5 May 2022
Replying to @FlorianWoh
Why we need an IOMMU and what is it anyway? Interesting talk by @SiFive at the #RISCV week in Paris
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.@Andes_Tech’s @FlorianWoh highlighted how #RISCV “goes BIG” as we’re seeing more high-end RISC-V cores on the market, adoption of RISC-V is skyrocketing, and RISC-V is entering new markets. #Spring2022RISCVWeek #RISCVEverywhere
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“RISC-V empowers our community to seize growing opportunities.” At #Spring2022RISCVWeek, #RISCV CEO @Calista_Redmond discussed how RISC-V is enabling innovation across industries, including automotive, consumer IoT devices, AI/ML, edge computing, and HPC. #RISCVEverywhere
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Together with my poster (@UNIMORE_univ @pulp_platform) at the #Spring2022RISCVWeek in #Paris! What an event! Many great people and exciting news from industry and academia have made this event a global success. No doubts: @risc_v is an inspiring and vibrant community to be in!
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Super excited of having joined #Spring2022RISCVWeek with my poster. @risc_v has an amazing and energetic community, proud to be part of it! @pulp_platform
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That's a wrap on #Spring2022RISCVWeek! Thank you for joining us for such a fun and packed few days of learning about #RISCV.
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Interested in graph analytics on #RISCV GPU? Curious about using the TUM Uncore environment for RISC-V for teaching, #AI and quantum computing? Join our second poster session and exhibition to learn all this and more. #Spring2022RISCVWeek
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At 10 a.m. CEST (1 a.m. PT), #RISCV'S @mark_riscv and @VRULLEU's Philipp Tomsich will provide an overview of existing software and ongoing initiatives to enable adoption of RISC-V for ISVs, software distributions and system vendors. hubs.la/Q019wkgK0 #Spring2022RISCVWeek

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Join @VRULLEU founder Philipp Tomsich at 9:40 a.m. CEST (12:40 a.m. PT) for a presentation on key initiatives to create a robust ecosystem for ISVs while unlocking the benefits of #RISCV’s mix-and-match approach to ISA customization: hubs.la/Q019wm900 #Spring2022RISCVWeek

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Happy #RISCV International Day! It's the final day of #Spring2022RISCVWeek. We are kicking things off at 9 a.m. CEST (12 a.m. PT) with an exciting State of the Union address from #RISCV CTO @mark_riscv. Come hear about RISC-V's achievements and plans: hubs.la/Q019wklj0

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4 May 2022
“In a world where Dennard scaling & Moore's law is ending, you need to use architectural innovation to succeed”. Zdeněk Přikryl presented at #Spring2022RISCVWeek @risc_v Download our latest whitepaper to learn how processor design is being redefined my.mtr.cool/zfuicmtqzs
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Day 2 of #Spring2022RISCVWeek has come to a close! Thank you to everyone for making it such an eventful day. We are excited to see everyone tomorrow for "RISC-V International Day" and the final day of our 3-day event.
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Curious about exploring #RISCV high performance compute clusters? Interested in hearing about composable custom extensions and function units for RISC-V? Come by the second #Spring2022RISCVWeek poster session to learn all this and more.
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Group is building #opensource, permissive, fully featured #RISCV IPs (called CORE-V). Join @DavideSchiavo10 at 2:30 p.m. CEST (5:30 a.m. PT) to learn more about the CORE-V roadmap and what's coming soon. hubs.la/Q019hkdf0 #Spring2022RISCVWeek
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#NaxRiscv is a recently developed OoO RV32/64 IMACSU softcore intended to provide better single threaded performances, keep logic resources usage reasonable, and more. Join @dolu1990 at 2:10 p.m. CEST (5:10 a.m. PT) to learn more. hubs.la/Q019hpQh0 #Spring2022RISCVWeek
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Attention, #Spring2022RISCVWeek attendees! The second poster session is in session. Come by to view all the informative #RISCV-related posters.
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Several EPI partners are participating at the #Spring2022RISCVWeek in Paris! 🥳 Francesco Minervini from @BSC_CNS is presenting Vitruvius, the Vector Processing Unit powering the Vector EPI Accelerator. 💪
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4 May 2022
This afternoon (14:25) at the @risc_v #Spring2022RISCVWeek @Codasip CTO Zdeněk Přikryl presents Customizing RISC-V designs to unlock innovation  Download our latest paper that looks in detail at what's next for processors: codasip.com/2022/04/08/semic…  #RISCV #DesignForDifferentiation
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Today at #Spring2022RISCVWeek - find out more about our roadmap of the CORE-V family of cores with @DavideSchiavo10. Followed by Jérôme Quévremont from @thalesgroup giving a review of the CVA6 core! (14h40 CEST) 🇨🇵 #OpenHWGroup #Thales #RISCV #OpenSourceHW
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