20 Photos and videos
A design from 2009
7 Sep 2023
Advertise your account with one PCB.
I'll start
ALT The RP2040 Stamp
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.@ATaylorFPGA's latest project looks at a simple AM modulation and demodulation scheme on an FPGA leveraging the @AMDembedded Vitis Model Composer. hackster.io/adam-taylor/am-m…
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The alpha version of my new book "Optimal Transport
for Machine Learners" is out, with in particular an online version with interactive figures
gpeyre.com/ot4ml/
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Ayoub Bouaddi is one of the standout talents at the World Cup 🇲🇦
The Moroccan midfielder had an impressive debut vs Brazil (stood tall against Casemiro, Fabinho & Paquetá).
Lille tied him down until 2029, but Premier League clubs are now circling. Big summer ahead!
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Jun 15
First production batch of the Forgix has arrived, our $50 simple FPGA Board. Get on the mailing list here forgix.tech/
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Jun 13
Digital microfluidics: The art of controlling droplets with electricity
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Jun 12
A free MIT course breaking down fundamental math concepts in computer science: bit.ly/4kXuqQ6
Here, MIT prof. Erik Demaine breaks down state machines (Lecture 4).
v/@MITOCW
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One of the aha moments I went through with Verilog HDL is that you're not writing a program, but describing a circuit. Took me time to develop intuition about what hardware my code was synthesising to on FPGA. Here's a classic example with blocking vs. non-blocking assignments:
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Jun 11
Ready to Fuzz USB stack like never, get an ESP32 and let's do it!
github.com/fuzzsociety/usbSt…
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Jun 12
I made a PCB business card that measures your heart rate: CARDio
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Jun 12
Maxwell -Boltzmann distribution from beads and a motor.
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If you're starting with FPGAs, take a look at implementing I2S - a simple, useful protocol to read data from an I2S mic or generate digital audio and send to an I2S amp. The spec provides reference circuits you can follow, or you can take the behavioral modeling approach. Spec:
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Jun 10
switching from x86 to ARM: ISE and iMPACT work well in QEMU, with FPGA build and JTAG working fine, although not as fast as a native x86! maybe it's because of the shared file system, not sure, I need to investigate more... 🤔
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In FPGA designs you will sometimes need a one clock pulse (called a strobe) at a lower frequency. Eg. baud rate generator for UART, I2S clock, etc. ZipCPU has a great technique for this which I have used many times: The Fractional Clock Divider. Read about it here:
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AI sucking the joy out of programming is making me turn to retro computers🙂. Here's an interesting 2004 student project from MIT:
The Design and Implementation of the Nintendo Entertainment System.
CPU PPU VGA implemented on FPGAs. PDF link:
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Jun 6
6/7 FPGA MSX
リセット信号関連でタイミング割れが発生してるので、リセット信号を叩いてる FF を分離してみるものの、
分離した新しい方を使っているにもかかわらず、もとからある方に繋がってるようなタイミングエラー表示のままで改善されなかった。
おそらく、論理的に同じだからと、GOWIN EDA が１つに統合してしまうのだろう・・ということで、
「勝手に統合するな！」という指示ができるのか？と Grokさんに聞いてみたら「できる」と教えてくれた。
なんと、コメントに /* synthesis syn_preserve = 1 */ とつければいいらしい。
Grokさんの嘘なんじゃね？と、半分疑いながら試してみたところ、、、正解だったようです。
リセット信号のタイミングエラーが全部解消しました😅
Grokさん、疑ってごめんなさい😖
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Jun 7
New in shrike-gen for @Vicharak_In 's Shrike-lite:
Experimental support for VHDL!
github.com/trholding/shrike-…
Credit: Marco (annoyedmilk) for the VHDL inspiration
@deeempak @AksharVastarpar Is the VHDL blink code correct? Builds fine, haven't tested yet.
#fpga #vhdl #verilog
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Jun 6
Integration by parts turns products of functions into simpler integrals.
If u(x) and v(x) are continuously differentiable, then ∫u dv = uv − ∫v du.
Use the ILATE rule to pick u: Inverse, Logarithmic, Algebraic, Trigonometric, Exponential.
Example: ∫(log x)⋅1 dx = x log x − x C.
Engineers rely on it to compute work from variable forces in physics and to solve signals in electrical and mechanical systems.
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Jun 6
Así funciona el algoritmo de Dijkstra
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